loadpatents
name:-0.030499935150146
name:-0.036401033401489
name:-0.015567064285278
Yao; Chih-Wei Patent Filings

Yao; Chih-Wei

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yao; Chih-Wei.The latest application filed is for "apparatus and method for automatic search of sub-sampling phase locked loop (ss-pll) locking acquisition".

Company Profile
13.32.25
  • Yao; Chih-Wei - Saratoga CA
  • Yao; Chih-Wei - Changhua County TW
  • Yao; Chih-Wei - Sunnyvale CA
  • - Sunnyvale CA US
  • Yao; Chih-Wei - Milpitas CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition
Grant 11,431,344 - Zuo , et al. August 30, 2
2022-08-30
Simulation method of an electron device
Grant 11,354,476 - Sano , et al. June 7, 2
2022-06-07
System and method for providing fast-settling quadrature detection and correction
Grant 11,233,627 - Huang , et al. January 25, 2
2022-01-25
System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)
Grant 11,175,633 - Yao , et al. November 16, 2
2021-11-16
Apparatus And Method For Automatic Search Of Sub-sampling Phase Locked Loop (ss-pll) Locking Acquisition
App 20210313995 - ZUO; Yongrong ;   et al.
2021-10-07
Ring voltage controlled oscillator (VCO) startup helper circuit
Grant 11,115,005 - Liu , et al. September 7, 2
2021-09-07
Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition
Grant 11,063,599 - Zuo , et al. July 13, 2
2021-07-13
Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit
Grant 11,050,428 - Huang , et al. June 29, 2
2021-06-29
System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)
Grant 10,996,634 - Yao , et al. May 4, 2
2021-05-04
Sigma-delta modulation quantization error reduction technique for fractional-N phase-locked loop (PLL)
Grant 10,965,297 - Wu , et al. March 30, 2
2021-03-30
Multiphase Injection Locked Sub-sampling Phase Locked Loop (pll) Circuit
App 20210067166 - LIU; Xiong ;   et al.
2021-03-04
Ring Voltage Controlled Oscillator (vco) Startup Helper Circuit
App 20210067145 - LIU; Xiong ;   et al.
2021-03-04
System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)
Grant 10,917,078 - Wu , et al. February 9, 2
2021-02-09
System And Method For Providing Fast-settling Quadrature Detection And Correction
App 20210028919 - Huang; Zhiqiang ;   et al.
2021-01-28
Synchronous Sampling In-phase And Quadrature-phase (i/q) Detection Circuit
App 20200403621 - HUANG; Zhiqiang ;   et al.
2020-12-24
System and method for providing fast-settling quadrature detection and correction
Grant 10,841,072 - Huang , et al. November 17, 2
2020-11-17
System And Method For Fast-converging Digital-to-time Converter (dtc) Gain Calibration For Dtc-based Analog Fractional-n Phase Lock Loop (pll)
App 20200348626 - YAO; Chih-Wei ;   et al.
2020-11-05
Apparatus And Method For Automatic Search Of Sub-sampling Phase Locked Loop (ss-pll) Locking Acquisition
App 20200343898 - ZUO; Yongrong ;   et al.
2020-10-29
Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit
Grant 10,812,088 - Huang , et al. October 20, 2
2020-10-20
System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)
Grant 10725432 -
2020-07-28
System And Method For Providing Fast-settling Quadrature Detection And Correction
App 20200186323 - Huang; Zhiqiang ;   et al.
2020-06-11
System And Method For Fast Converging Reference Clock Duty Cycle Correction For Digital To Time Converter (dtc)-based Analog Fra
App 20200177173 - WU; Wanghua ;   et al.
2020-06-04
Simulation method of an electron device
App 20200159881 - Sano; Nobuyuki ;   et al.
2020-05-21
System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to- digital converter (TDC)
Grant 10,623,010 - Loke , et al.
2020-04-14
Synchronous Sampling In-phase And Quadrature-phase (i/q) Detection Circuit
App 20200099380 - HUANG; Zhiqiang ;   et al.
2020-03-26
System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)
Grant 10,581,418 - Wu , et al.
2020-03-03
System And Method For Calibrating Pulse Width And Delay
App 20200014374 - Loke; Wing-Fai ;   et al.
2020-01-09
System and method for calibrating pulse width and delay
Grant 10,418,981 - Loke , et al. Sept
2019-09-17
System And Method For Fast-converging Digital-to-time Converter (dtc) Gain Calibration For Dtc-based Analog Fractional-n Phase L
App 20190212703 - YAO; Chih-Wei ;   et al.
2019-07-11
System And Method For Fast Converging Reference Clock Duty Cycle Correction For Digital To Time Converter (dtc)-based Analog Fra
App 20190214976 - Wu; Wanghua ;   et al.
2019-07-11
System And Method Of Calibrating Input Signal To Successive Approximation Register (sar) Analog-to-digital Converter (adc) In Adc-assisted Time-to-digital Converter (tdc)
App 20180309459 - LOKE; Wing-Fai ;   et al.
2018-10-25
System And Method For Calibrating Pulse Width And Delay
App 20180302069 - Loke; Wing-Fai ;   et al.
2018-10-18
System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to-digital converter (TDC)
Grant 10,009,036 - Loke , et al. June 26, 2
2018-06-26
System And Method Of Calibrating Input Signal To Successive Approximation Register (sar) Analog-to-digital Converter (adc) In Adc-assisted Time-to-digital Converter (tdc)
App 20180076821 - LOKE; Wing-Fai ;   et al.
2018-03-15
System and method for time-to-digital converter fine-conversion using analog-to-digital converter (ADC)
Grant 9,746,832 - Yao August 29, 2
2017-08-29
Fine tuning control apparatus and method
Grant 9,595,915 - Loke , et al. March 14, 2
2017-03-14
Fine Tuning Control Apparatus And Method
App 20160276978 - Loke; Wing Fai ;   et al.
2016-09-22
System and method using temperature tracking for a controlled oscillator
Grant 9,379,662 - Loke , et al. June 28, 2
2016-06-28
Fine tuning control for a digitally controlled oscillator
Grant 9,356,555 - Loke , et al. May 31, 2
2016-05-31
System And Method Using Temperature Tracking For A Controlled Oscillator
App 20160079918 - LOKE; Wing Fai ;   et al.
2016-03-17
Fine Tuning Control For A Digitally Controlled Oscillator
App 20160079919 - LOKE; Wing Fai ;   et al.
2016-03-17
Communication system with frequency synthesis mechanism and method of operation thereof
Grant 9,240,914 - Yao January 19, 2
2016-01-19
Reference clock compensation for fractional-N phase lock loops (PLLS)
Grant 9,219,484 - Yao December 22, 2
2015-12-22
High resolution sampling-based time to digital converter
Grant 8,970,421 - Gao , et al. March 3, 2
2015-03-03
Reference Clock Compensation For Fractional-n Phase Lock Loops (plls)
App 20140240012 - Yao; Chih-Wei
2014-08-28
Communication System With Frequency Synthesis Mechanism And Method Of Operation Thereof
App 20140198884 - Yao; Chih-Wei
2014-07-17
Reference clock compensation for fractional-N phase lock loops (PLLs)
Grant 8,717,074 - Yao May 6, 2
2014-05-06
Reference Clock Compensation For Fractional-n Phase Lock Loops (plls)
App 20140035637 - Yao; Chih-Wei
2014-02-06
Circuit and circuit methods for reduction of PFD noise contribution for ADPLL
Grant 8,604,849 - Yao December 10, 2
2013-12-10
Reference clock compensation for fractional-N phase lock loops (PLLs)
Grant 8,564,342 - Yao October 22, 2
2013-10-22
High resolution sampling-based time to digital converter
Grant 8,564,471 - Gao , et al. October 22, 2
2013-10-22
Circuit and circuit method for reduction of PFD noise contribution for ADPLL
Grant 8,461,886 - Yao June 11, 2
2013-06-11
Reference Clock Compensation for Fractional-N Phase Lock Loops (PLLs)
App 20120200328 - Yao; Chih-Wei
2012-08-09
Low phase-noise oscillator
Grant 7,847,650 - Yao , et al. December 7, 2
2010-12-07
Low Phase-Noise Oscillator
App 20080143446 - Yao; Chih-Wei ;   et al.
2008-06-19

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