loadpatents
Patent applications and USPTO patent grants for Yao; Chih-Tsung.The latest application filed is for "clock tree circuit and memory controller".
Patent | Date |
---|---|
Wiring layout having differently shaped vias Grant 9,685,395 - Chuang , et al. June 20, 2 | 2017-06-20 |
Clock tree circuit and memory controller Grant 9,557,764 - Chiang , et al. January 31, 2 | 2017-01-31 |
Clock Tree Circuit And Memory Controller App 20160132071 - CHIANG; Chen-Feng ;   et al. | 2016-05-12 |
Clock tree circuit and memory controller Grant 9,256,245 - Chiang , et al. February 9, 2 | 2016-02-09 |
Clock Tree Circuit And Memory Controller App 20150286243 - CHIANG; Chen-Feng ;   et al. | 2015-10-08 |
Wiring Layout Having Differently Shaped Vias App 20150179550 - Chuang; Harry-Hak-Lay ;   et al. | 2015-06-25 |
Wiring layout having differently shaped vias Grant 8,981,562 - Chuang , et al. March 17, 2 | 2015-03-17 |
Method of generating technology file for integrated circuit design tools Grant 8,826,207 - Hou , et al. September 2, 2 | 2014-09-02 |
3-dimensional device design layout Grant 8,286,114 - Chuang , et al. October 9, 2 | 2012-10-09 |
Method of Generating Technology File for Integrated Circuit Design Tools App 20090077507 - Hou; Cliff ;   et al. | 2009-03-19 |
3-Dimensional Device Design Layout App 20080263492 - Chuang; Harry ;   et al. | 2008-10-23 |
Method for Improving Design Window App 20080237885 - Chuang; Harry ;   et al. | 2008-10-02 |
Method for improving design window Grant 7,404,167 - Chuang , et al. July 22, 2 | 2008-07-22 |
Method for improving design window App 20060188824 - Chuang; Harry ;   et al. | 2006-08-24 |
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