Yang; Wenge

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Wenge.The latest application filed is for "controlling critical dimensions of structures formed on a wafer in semiconductor processing".

Company Profile

0.20.2

Yang; Wenge - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Controlling critical dimensions of structures formed on a wafer in semiconductor processing Grant 7,566,181 - Yang , et al. July 28, 2	2009-07-28
Method of forming highly conductive semiconductor structures via plasma etch Grant 7,217,652 - Yang May 15, 2	2007-05-15
Controlling critical dimensions of structures formed on a wafer in semiconductor processing App 20060046166 - Yang; Wenge ; et al.	2006-03-02
Method for forming SAC using a dielectric as a BARC and FICD enlarger Grant 6,878,622 - Yang , et al. April 12, 2	2005-04-12
Combined optical profilometry and projection microscopy of integrated circuit structures Grant 6,645,824 - Yang , et al. November 11, 2	2003-11-11
Combined Optical Profilometry And Projection Microscopy Of Integrated Circuit Structures App 20030203590 - Yang, Wenge ; et al.	2003-10-30
Method for fabricating a conductive structure for a semiconductor device Grant 6,627,526 - Yang , et al. September 30, 2	2003-09-30
Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers Grant 6,596,623 - Subramanian , et al. July 22, 2	2003-07-22
Semiconductor devices with reduced control gate dimensions Grant 6,515,328 - Yang , et al. February 4, 2	2003-02-04
Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process Grant 6,482,699 - Hu , et al. November 19, 2	2002-11-19
Method of fabricating a shallow trench isolation structure with reduced topography Grant 6,423,612 - Yang , et al. July 23, 2	2002-07-23
Method to produce small space pattern using plasma polymerization layer Grant 6,416,933 - Singh , et al. July 9, 2	2002-07-09
Method for etching memory gate stack using thin resist layer Grant 6,383,939 - Yang , et al. May 7, 2	2002-05-07
Method for trimming a photoresist pattern line for memory gate etching Grant 6,372,651 - Yang , et al. April 16, 2	2002-04-16
Method for forming self-aligned contacts and interconnection lines using dual damascene techniques Grant 6,359,307 - Wang , et al. March 19, 2	2002-03-19
Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer Grant 6,306,713 - Hu , et al. October 23, 2	2001-10-23
Method for removing anti-reflective coating layer using plasma etch process before contact CMP Grant 6,291,296 - Hui , et al. September 18, 2	2001-09-18
RTA methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile Grant 6,218,310 - Shen , et al. April 17, 2	2001-04-17
Method for etching layers on a semiconductor wafer in a single etching chamber Grant 6,159,860 - Yang , et al. December 12, 2	2000-12-12
Methods for removing silicide residue in a semiconductor device Grant 6,159,794 - Yang , et al. December 12, 2	2000-12-12
Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride Grant 6,110,779 - Yang , et al. August 29, 2	2000-08-29
Methods and arrangements for forming a tapered floating gate in non-volatile memory semiconductor devices Grant 5,973,353 - Yang , et al. October 26, 1	1999-10-26

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