Yang; Szu-Hung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Szu-Hung.The latest application filed is for "plating apparatus and method for electroplating wafer".

Company Profile

0.12.9

Yang; Szu-Hung - Tainan TW
Yang; Szu-Hung - Tainan City TW
Yang; Szu-Hung - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Plating apparatus and method for electroplating wafer Grant 11,401,624 - Lin , et al. August 2, 2	2022-08-02
Plating Apparatus And Method For Electroplating Wafer App 20220025540 - Lin; Che-Min ; et al.	2022-01-27
CMOS image sensor structure with crosstalk improvement Grant 10,957,728 - Chang , et al. March 23, 2	2021-03-23
CMOS image sensor structure with crosstalk improvement Grant 10,367,019 - Chang , et al. July 30, 2	2019-07-30
Cmos Image Sensor Structure With Crosstalk Improvement App 20190127036 - CHANG; Hung-Chang ; et al.	2019-05-02
Semiconductor structure and method of forming the same Grant 9,515,021 - Chen , et al. December 6, 2	2016-12-06
Cmos Image Sensor Structure With Crosstalk Improvement App 20160225810 - CHANG; Hung-Chang ; et al.	2016-08-04
Methods for achieving width control in etching processes Grant 9,040,317 - Liao , et al. May 26, 2	2015-05-26
Dual profile shallow trench isolation apparatus and system Grant 8,872,301 - Hung , et al. October 28, 2	2014-10-28
Structures for grounding metal shields in backside illumination image sensor chips Grant 8,803,271 - Liu , et al. August 12, 2	2014-08-12
Dual Profile Shallow Trench Isolation Apparatus and System App 20130277790 - Hung; Chia-Yang ; et al.	2013-10-24
Methods for Achieving Width Control in Etching Processes App 20130252355 - Liao; Keng-Ying ; et al.	2013-09-26
Structures for Grounding Metal Shields in Backside Illumination Image Sensor Chips App 20130249040 - Liu; Zhe-Ju ; et al.	2013-09-26
Plasma etch method for forming uniform linewidth residue free patterned composite silicon containing dielectric layer/silicon stack layer Grant 6,686,292 - Yang , et al. February 3, 2	2004-02-03
Method for forming corrosion inhibited conductor layer Grant 6,682,659 - Cho , et al. January 27, 2	2004-01-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.