Yang; Simon Shi-Ning

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Simon Shi-Ning.The latest application filed is for "three-dimensional memory devices having a plurality of nand strings".

Company Profile

13.14.18

Yang; Simon Shi-Ning - Hubei CN
Yang; Simon Shi-Ning - Wuhan CN
Yang; Simon Shi-ning - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Source structure of three-dimensional memory device and method for forming the same Grant 11,264,397 - Hu , et al. March 1, 2	2022-03-01
Three-dimensional memory devices and methods for forming the same Grant 11,211,397 - Lu , et al. December 28, 2	2021-12-28
Three-dimensional Memory Devices Having A Plurality Of Nand Strings App 20210296341 - ZHU; Jifeng ; et al.	2021-09-23
Three-dimensional memory devices having a plurality of NAND strings Grant 11,031,333 - Zhu , et al. June 8, 2	2021-06-08
Hybrid Bonding Contact Structure Of Three-dimensional Memory Device App 20210134826 - LU; Zhenyu ; et al.	2021-05-06
Structure and method for testing three-dimensional memory device Grant 10,998,079 - Kim , et al. May 4, 2	2021-05-04
Three-Dimensional Memory Devices and Methods for Forming the Same App 20210098491 - LU; Zhenyu ; et al.	2021-04-01
Hybrid bonding contact structure of three-dimensional memory device Grant 10,923,491 - Lu , et al. February 16, 2	2021-02-16
Source Structure Of Three-dimensional Memory Device And Method For Forming The Same App 20210005621 - HU; Yushi ; et al.	2021-01-07
Source structure of three-dimensional memory device and method for forming the same Grant 10,804,279 - Hu , et al. October 13, 2	2020-10-13
Hybrid Bonding Contact Structure Of Three-dimensional Memory Device App 20200295025 - LU; Zhenyu ; et al.	2020-09-17
Structure And Method For Testing Three-dimensional Memory Device App 20200265913 - KIM; Jong Jun ; et al.	2020-08-20
Staircase Etch Control In Forming Three-dimensional Memory Device App 20200203285 - LU; Zhenyu ; et al.	2020-06-25
Structure and method for testing three-dimensional memory device Grant 10,679,721 - Kim , et al.	2020-06-09
Hybrid bonding contact structure of three-dimensional memory device Grant 10,593,690 - Lu , et al.	2020-03-17
Staircase etch control in forming three-dimensional memory device Grant 10,522,474 - Lu , et al. Dec	2019-12-31
Low-dropout regulators Grant 10,423,176 - Pan , et al. Sept	2019-09-24
Three-dimensional Memory Devices Having A Plurality Of Nand Strings App 20190244893 - ZHU; Jifeng ; et al.	2019-08-08
Three-dimensional Memory Devices Having A Plurality Of Nand Strings App 20190244892 - Zhu; Jifeng ; et al.	2019-08-08
Source Structure Of Three-dimensional Memory Device And Method For Forming The Same App 20190164983 - HU; Yushi ; et al.	2019-05-30
Three-dimensional memory devices having a plurality of NAND strings Grant 10,283,452 - Zhu , et al.	2019-05-07
Three-Dimensional Memory Devices and Methods for Forming the Same App 20190088589 - ZHU; Jifeng ; et al.	2019-03-21
Three-dimensional Memory Devices And Methods For Forming The Same App 20190081069 - LU; Zhenyu ; et al.	2019-03-14
Low-dropout Regulators App 20190064862 - PAN; Feng ; et al.	2019-02-28
Structure And Method For Testing Three-dimensional Memory Device App 20190057756 - Kim; Jong Jun ; et al.	2019-02-21
Hybrid Bonding Contact Structure Of Three-dimensional Memory Device App 20190057974 - LU; Zhenyu ; et al.	2019-02-21
Staircase Etch Control In Forming Three-dimensional Memory Device App 20190051610 - LU; Zhenyu ; et al.	2019-02-14
Source structure of three-dimensional memory device and method for forming the same Grant 10,147,732 - Hu , et al. De	2018-12-04
Method for processing IC designs for different metal BEOL processes Grant 7,442,637 - Su , et al. October 28, 2	2008-10-28
Method for using a Cu BEOL process to fabricate an integrated circuit (IC) originally having an al design Grant 7,381,646 - Su , et al. June 3, 2	2008-06-03
A Method For Processing Ic Designs For Different Metal Beol Processes App 20070037384 - Su; Jiannong ; et al.	2007-02-15
A Method For Using A Cu Beol Process To Fabricate An Integrated Circuit (ic) Originally Having An Al Design App 20070037394 - Su; Jiannong ; et al.	2007-02-15

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