loadpatents
Patent applications and USPTO patent grants for Yang; Shih Kuang.The latest application filed is for "through-substrate-via with reentrant profile".
Patent | Date |
---|---|
Through-substrate-via With Reentrant Profile App 20220084908 - Shih; Hung-Ling ;   et al. | 2022-03-17 |
Device-region Layout For Embedded Flash App 20220044729 - Yang; Shih Kuang ;   et al. | 2022-02-10 |
Control Gate Strap Layout To Improve A Word Line Etch Process Window App 20210399103 - Hsu; Yu-Ling ;   et al. | 2021-12-23 |
Method to reduce kink effect in semiconductor devices Grant 11,189,627 - Shih , et al. November 30, 2 | 2021-11-30 |
Device-region layout for embedded flash Grant 11,158,377 - Yang , et al. October 26, 2 | 2021-10-26 |
Control gate strap layout to improve a word line etch process window Grant 11,127,827 - Hsu , et al. September 21, 2 | 2021-09-21 |
Strap-cell Architecture For Embedded Memory App 20210183875 - Huang; Wen-Tuo ;   et al. | 2021-06-17 |
Device-region Layout For Embedded Flash App 20210074360 - Yang; Shih Kuang ;   et al. | 2021-03-11 |
Strap-cell architecture for embedded memory Grant 10,943,913 - Huang , et al. March 9, 2 | 2021-03-09 |
Device-region layout for embedded flash Grant 10,861,553 - Yang , et al. December 8, 2 | 2020-12-08 |
Method To Reduce Kink Effect In Semiconductor Devices App 20200219892 - Shih; Hung-Ling ;   et al. | 2020-07-09 |
Method to reduce kink effect in semiconductor devices Grant 10,680,002 - Shih , et al. | 2020-06-09 |
Strap-cell Architecture For Embedded Memory App 20200105775 - Huang; Wen-Tuo ;   et al. | 2020-04-02 |
Device-region Layout For Embedded Flash App 20200105346 - Yang; Shih Kuang ;   et al. | 2020-04-02 |
Control Gate Strap Layout To Improve A Word Line Etch Process Window App 20200098877 - Hsu; Yu-Ling ;   et al. | 2020-03-26 |
Method To Reduce Kink Effect In Semiconductor Devices App 20190355731 - Shih; Hung-Ling ;   et al. | 2019-11-21 |
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