Yang; Jean Yee-Mei

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Jean Yee-Mei.The latest application filed is for "memory device protection layer".

Company Profile

0.25.8

Yang; Jean Yee-Mei - Glendale CA
Yang; Jean Yee-Mei - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dielectric extension to mitigate short channel effects Grant 9,318,333 - Gopal , et al. April 19, 2	2016-04-19
Memory Device Protection Layer App 20130228851 - Sugino; Rinji ; et al.	2013-09-05
Memory device protection layer Grant 8,415,734 - Sugino , et al. April 9, 2	2013-04-09
Thin oxide dummy tiling as charge protection Grant 7,977,218 - Chen , et al. July 12, 2	2011-07-12
Using implanted poly-1 to improve charging protection in dual-poly process Grant 7,553,727 - Kwan , et al. June 30, 2	2009-06-30
Dielectric extension to mitigate short channel effects App 20080157199 - Gopal; Vidyut ; et al.	2008-07-03
Thin oxide dummy tiling as charge protection App 20080153269 - Chen; Cinti ; et al.	2008-06-26
Using implanted poly-1 to improve charging protection in dual-poly process App 20080150006 - Kwan; Ming-Sang ; et al.	2008-06-26
Memory Device Protection Layer App 20080135913 - Sugino; Rinji ; et al.	2008-06-12
Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device Grant 7,163,860 - Kamal , et al. January 16, 2	2007-01-16
Alignment marks with salicided spacers between bitlines for alignment signal improvement Grant 7,098,546 - Lingunis , et al. August 29, 2	2006-08-29
Memory structure having tunable interlayer dielectric and method for fabricating same Grant 7,078,749 - Yang , et al. July 18, 2	2006-07-18
Method for forming wordlines having irregular spacing in a memory array Grant 7,052,961 - Shiraiwa , et al. May 30, 2	2006-05-30
Undoped oxide liner/BPSG for improved data retention Grant 7,023,046 - Ngo , et al. April 4, 2	2006-04-04
Bitline implant utilizing dual poly Grant 6,989,320 - Qian , et al. January 24, 2	2006-01-24
Memory device having silicided bitlines and method of forming the same Grant 6,987,048 - Cheng , et al. January 17, 2	2006-01-17
Bitline implant utilizing dual poly App 20050255651 - Qian, Weidong ; et al.	2005-11-17
Multi-bit silicon nitride charge-trapping non-volatile memory cell Grant 6,897,533 - Yang , et al. May 24, 2	2005-05-24
Method and structure for protecting NROM devices from induced charge damage during device fabrication Grant 6,869,844 - Liu , et al. March 22, 2	2005-03-22
Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance Grant 6,855,608 - Ramsbey , et al. February 15, 2	2005-02-15
Undoped oxide liner/BPSG for improved data retention App 20050006693 - Ngo, Minh Van ; et al.	2005-01-13
Methods for fabricating and planarizing dual poly scalable SONOS flash memory Grant 6,797,565 - Yang , et al. September 28, 2	2004-09-28
Structure and method for suppressing oxide encroachment in a floating gate memory cell Grant 6,767,791 - Wu , et al. July 27, 2	2004-07-27
Memory array having shallow bit line with silicide contact portion and method of formation Grant 6,744,105 - Chen , et al. June 1, 2	2004-06-01
Structure and method for reducing charge loss in a memory cell Grant 6,737,701 - Tu , et al. May 18, 2	2004-05-18
Dummy wordline for erase and bitline leakage Grant 6,707,078 - Shiraiwa , et al. March 16, 2	2004-03-16
Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory Grant 6,680,509 - Wu , et al. January 20, 2	2004-01-20
Alignment system for planar charge trapping dielectric memory cell lithography Grant 6,667,212 - Shiraiwa , et al. December 23, 2	2003-12-23
Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory Grant 6,440,797 - Wu , et al. August 27, 2	2002-08-27
Source drain implant during ONO formation for improved isolation of SONOS devices Grant 6,436,768 - Yang , et al. August 20, 2	2002-08-20

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