Yang; Haining S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Haining S..The latest application filed is for "cmos devices with stressed channel regions, and methods for fabricating the same".

Company Profile

0.160.173

Yang; Haining S. - San Diego CA
Yang; Haining S. - Wappingers Falls NY
Yang; Haining S - Wappingers Falls NY US
Yang; Haining S. - Wappinger Falls NY
Yang; Haining S. - Hopewell Junction NY
YANG; HAINING S. - Wappingers NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor devices having tensile and/or compressive stress and methods of manufacturing Grant 9,431,535 - Dyer , et al. August 30, 2	2016-08-30
Semiconductor devices having tensile and/or compressive stress and methods of manufacturing Grant 9,276,111 - Dyer , et al. March 1, 2	2016-03-01
Electrical fuse and method of making Grant 9,059,171 - Yang , et al. June 16, 2	2015-06-16
Cmos Devices With Stressed Channel Regions, And Methods For Fabricating The Same App 20150162446 - Chen; Xiangdong ; et al.	2015-06-11
Heterojunction tunneling field effect transistors, and methods for fabricating the same Grant 9,040,960 - Chen , et al. May 26, 2	2015-05-26
Method and structure for controlling stress in a transistor channel Grant 9,006,836 - Yang , et al. April 14, 2	2015-04-14
Semiconductor Devices Having Tensile And/or Compressive Stress And Methods Of Manufacturing App 20150054028 - DYER; Thomas W. ; et al.	2015-02-26
Semiconductor Devices Having Tensile And/or Compressive Stress And Methods Of Manufacturing App 20150037957 - Dyer; Thomas W. ; et al.	2015-02-05
Semiconductor devices having tensile and/or compressive stress and methods of manufacturing Grant 8,896,069 - Dyer , et al. November 25, 2	2014-11-25
Semiconductor devices having tensile and/or compressive stress and methods of manufacturing Grant 8,889,504 - Dyer , et al. November 18, 2	2014-11-18
CMOS devices with stressed channel regions, and methods for fabricating the same Grant 8,853,746 - Chen , et al. October 7, 2	2014-10-07
Structure and method for making low leakage and low mismatch NMOSFET Grant 8,836,044 - Wang , et al. September 16, 2	2014-09-16
Structure and method to form e-fuse with enhanced current crowding Grant 8,829,645 - Kim , et al. September 9, 2	2014-09-09
Body contacts for FET in SOI SRAM array Grant 8,809,187 - Tan , et al. August 19, 2	2014-08-19
Gate conductor with a diffusion barrier Grant 8,809,915 - Li , et al. August 19, 2	2014-08-19
Structure and method to form E-fuse with enhanced current crowding Grant 8,809,142 - Kim , et al. August 19, 2	2014-08-19
Hybrid interconnect structure for performance improvement and reliability enhancement Grant 8,796,854 - Yang , et al. August 5, 2	2014-08-05
Replacement gate CMOS Grant 8,765,558 - Cheng , et al. July 1, 2	2014-07-01
Hybrid interconnect structure for performance improvement and reliability enhancement Grant 8,753,979 - Yang , et al. June 17, 2	2014-06-17
Hybrid interconnect structure for performance improvement and reliability enhancement Grant 8,754,526 - Yang , et al. June 17, 2	2014-06-17
Heterojunction Tunneling Field Effect Transistors, And Methods For Fabricating The Same App 20140151644 - Chen; Xiangdong ; et al.	2014-06-05
Structure and method for making low leakage and low mismatch NMOSFET Grant 8,697,521 - Wang , et al. April 15, 2	2014-04-15
Structure and method of forming a transistor with asymmetric channel and source/drain regions Grant 8,674,444 - Yang , et al. March 18, 2	2014-03-18
Body Contacts For Fet In Soi Sram Array App 20140027851 - Tan; Yue ; et al.	2014-01-30
Replacement gate CMOS Grant 8,629,506 - Cheng , et al. January 14, 2	2014-01-14
Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts Grant 8,587,062 - Mandelman , et al. November 19, 2	2013-11-19
Electrical Fuse And Method Of Making App 20130277796 - YANG; Chih-Chao ; et al.	2013-10-24
Hybrid Interconnect Structure For Performance Improvement And Reliability Enhancement App 20130230983 - Yang; Chih-Chao ; et al.	2013-09-05
Gate conductor with a diffusion barrier App 20130228900 - Li; Wai-Kin ; et al.	2013-09-05
Hybrid Interconnect Structure For Performance Improvement And Reliability Enhancement App 20130228925 - Yang; Chih-Chao ; et al.	2013-09-05
Hybrid Interconnect Structure For Performance Improvement And Reliability Enhancement App 20130221529 - Yang; Chih-Chao ; et al.	2013-08-29
Electrical fuses and resistors having sublithographic dimensions Grant 8,513,769 - Black , et al. August 20, 2	2013-08-20
Structure And Method For Making Low Leakage And Low Mismatch Nmosfet App 20130193523 - Wang; Xinlin ; et al.	2013-08-01
Electrical fuse and method of making Grant 8,492,871 - Yang , et al. July 23, 2	2013-07-23
Semiconductor transistors having reduced distances between gate electrode regions Grant 8,476,717 - Wong , et al. July 2, 2	2013-07-02
Carrier mobility enhanced channel devices and method of manufacture Grant 8,461,625 - Cheng , et al. June 11, 2	2013-06-11
Hybrid interconnect structure for performance improvement and reliability enhancement Grant 8,456,006 - Yang , et al. June 4, 2	2013-06-04
Heterojunction tunneling field effect transistors, and methods for fabricating the same Grant 8,441,000 - Chen , et al. May 14, 2	2013-05-14
Boost cell supply write assist Grant 8,432,764 - Heymann , et al. April 30, 2	2013-04-30
High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same Grant 8,405,131 - Yang March 26, 2	2013-03-26
Method for reducing tip-to-tip spacing between lines Grant 8,361,704 - Colburn , et al. January 29, 2	2013-01-29
Body contacts for FET in SOI SRAM array Grant 8,338,292 - Tan , et al. December 25, 2	2012-12-25
Semiconductor devices having tensile and/or compressive stress and methods of manufacturing Grant 8,293,631 - Dyer , et al. October 23, 2	2012-10-23
Structure And Method Of Forming A Transistor With Asymmetric Channel And Source/drain Regions App 20120235236 - Yang; Haining S. ; et al.	2012-09-20
Structure And Method To Form E-fuse With Enhanced Current Crowding App 20120214301 - Kim; Deok-Kee ; et al.	2012-08-23
Heterojunction Tunneling Field Effect Transistors, And Methods For Fabricating The Same App 20120193679 - Chen; Xiangdong ; et al.	2012-08-02
Structure and method of forming a transistor with asymmetric channel and source/drain regions Grant 8,232,150 - Yang , et al. July 31, 2	2012-07-31
Double patterning process for integrated circuit device manufacturing Grant 8,232,210 - Cheng , et al. July 31, 2	2012-07-31
CMOS diodes with dual gate conductors, and methods for forming the same Grant 8,222,702 - Onsongo , et al. July 17, 2	2012-07-17
Semiconductor Devices Having Tensile And/or Compressive Stress And Methods Of Manufacturing App 20120175640 - DYER; Thomas W. ; et al.	2012-07-12
Replacement Gate Cmos App 20120178227 - Cheng; Kangguo ; et al.	2012-07-12
Field effect device including recessed and aligned germanium containing channel Grant 8,217,470 - Chen , et al. July 10, 2	2012-07-10
Semiconductor Devices Having Tensile And/or Compressive Stress And Methods Of Manufacturing App 20120135591 - DYER; Thomas W. ; et al.	2012-05-31
Semiconductor Transistors Having Reduced Distances Between Gate Electrode Regions App 20120126339 - Wong; Robert C. ; et al.	2012-05-24
Programmable PN anti-fuse Grant 8,178,945 - Wang , et al. May 15, 2	2012-05-15
Semiconductor transistors having reduced distances between gate electrode regions Grant 8,173,532 - Wong , et al. May 8, 2	2012-05-08
SOI substrates and SOI devices, and methods for forming the same Grant 8,159,031 - Dyer , et al. April 17, 2	2012-04-17
Multiwalled carbon nanotube memory device Grant 8,093,644 - Yang January 10, 2	2012-01-10
Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques Grant 8,083,958 - Li , et al. December 27, 2	2011-12-27
Boost Cell Supply Write Assist App 20110280094 - Heymann; Omer ; et al.	2011-11-17
Hybrid Interconnect Structure For Performance Improvement And Reliability Enhancement App 20110260323 - Yang; Chih-Chao ; et al.	2011-10-27
Structure and method to form dual silicide e-fuse Grant 8,013,419 - Kim , et al. September 6, 2	2011-09-06
Carrier Mobility Enhanced Channel Devices And Method Of Manufacture App 20110180853 - CHENG; Kangguo ; et al.	2011-07-28
Structure And Method For Making Low Leakage And Low Mismatch Nmosfet App 20110175170 - Wang; Xinlin ; et al.	2011-07-21
Hybrid interconnect structure for performance improvement and reliability enhancement Grant 7,973,409 - Yang , et al. July 5, 2	2011-07-05
Complementary field effect transistors having embedded silicon source and drain regions Grant 7,968,910 - Chen , et al. June 28, 2	2011-06-28
Carrier mobility enhanced channel devices and method of manufacture Grant 7,964,487 - Cheng , et al. June 21, 2	2011-06-21
Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance Grant 7,960,223 - Chen , et al. June 14, 2	2011-06-14
High aspect ratio electroplated metal feature and method Grant 7,951,714 - Edelstein , et al. May 31, 2	2011-05-31
Heterojunction tunneling field effect transistors, and methods for fabricating the same Grant 7,947,557 - Chen , et al. May 24, 2	2011-05-24
Method for dual stress liner Grant 7,943,454 - Chen , et al. May 17, 2	2011-05-17
Semiconductor device structure having enhanced performance FET device Grant 7,935,993 - Chen , et al. May 3, 2	2011-05-03
Method and structure for forming strained SI for CMOS devices Grant 7,928,443 - Steegen , et al. April 19, 2	2011-04-19
Double Patterning Process For Integrated Circuit Device Manufacturing App 20110070739 - Cheng; Kangguo ; et al.	2011-03-24
Hybrid orientation substrate and method for fabrication thereof Grant 7,892,899 - Yang , et al. February 22, 2	2011-02-22
High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching Grant 7,884,448 - Dyer , et al. February 8, 2	2011-02-08
Method and structure for relieving transistor performance degradation due to shallow trench isolation induced stress Grant 7,871,895 - Divakaruni , et al. January 18, 2	2011-01-18
Method of forming an SOI substrate contact Grant 7,867,893 - Yang , et al. January 11, 2	2011-01-11
Electrical fuse and method of making Grant 7,867,832 - Yang , et al. January 11, 2	2011-01-11
Dual oxide stress liner Grant 7,863,646 - Belyansky , et al. January 4, 2	2011-01-04
Method of enhancing hole mobility Grant 7,863,653 - Utomo , et al. January 4, 2	2011-01-04
Partially gated FINFET with gate dielectric on only one sidewall Grant 7,859,044 - Wong , et al. December 28, 2	2010-12-28
Methods and systems involving electrically programmable fuses Grant 7,851,885 - Kim , et al. December 14, 2	2010-12-14
Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost Grant 7,842,940 - de Souza , et al. November 30, 2	2010-11-30
Programmable Pn Anti-fuse App 20100295132 - Wang; Ping-Chuan ; et al.	2010-11-25
Metal gate compatible flash memory gate stack Grant 7,834,387 - Booth, Jr. , et al. November 16, 2	2010-11-16
Electrical Fuses And Resistors Having Sublithographic Dimensions App 20100283121 - Black; Charles T. ; et al.	2010-11-11
Electrical fuse having a cavity thereupon Grant 7,825,490 - Kim , et al. November 2, 2	2010-11-02
Cmos Diodes With Dual Gate Conductors, And Methods For Forming The Same App 20100252881 - Onsongo; David M. ; et al.	2010-10-07
Replacement Gate Cmos App 20100237424 - CHENG; KANGGUO ; et al.	2010-09-23
Methods And Systems Involving Electrically Programmable Fuses App 20100237460 - Kim; Deok-kee ; et al.	2010-09-23
Metal silicide alloy local interconnect Grant 7,791,109 - Wann , et al. September 7, 2	2010-09-07
Method and apparatus for increase strain effect in a transistor channel Grant 7,790,558 - Yang , et al. September 7, 2	2010-09-07
Electrical fuse having sublithographic cavities thereupon Grant 7,785,937 - Kim , et al. August 31, 2	2010-08-31
Sub-lithographic gate length transistor using self-assembling polymers Grant 7,786,527 - Yang , et al. August 31, 2	2010-08-31
Device patterned with sub-lithographic features with variable widths Grant 7,781,847 - Yang August 24, 2	2010-08-24
Body Contacts For Fet In Soi Sram Array App 20100207213 - Tan; Yue ; et al.	2010-08-19
Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link Grant 7,777,296 - Yang , et al. August 17, 2	2010-08-17
Non-planar fuse structure including angular bend Grant 7,777,297 - Yang , et al. August 17, 2	2010-08-17
Field Effect Device Includng Recessed And Aligned Germanium Containing Channel App 20100200934 - Chen; Xiangdong ; et al.	2010-08-12
Sub-lithographic interconnect patterning using self-assembling polymers Grant 7,767,099 - Li , et al. August 3, 2	2010-08-03
Method To Increase Strain Enhancement With Spacerless Fet And Dual Liner Process App 20100187636 - Yang; Haining S. ; et al.	2010-07-29
Structure And Method Of Forming A Transistor With Asymmetric Channel And Source/drain Regions App 20100176450 - Yang; Haining S. ; et al.	2010-07-15
Method For Reducing Tip-to-tip Spacing Between Lines App 20100178615 - COLBURN; MATTHEW E. ; et al.	2010-07-15
Self-aligned and extended inter-well isolation structure Grant 7,750,429 - Dyer , et al. July 6, 2	2010-07-06
Low contact resistance metal contact Grant 7,749,890 - Wong , et al. July 6, 2	2010-07-06
Dual workfunction silicide diode Grant 7,741,217 - Yang , et al. June 22, 2	2010-06-22
Electrical fuses and resistors having sublithographic dimensions Grant 7,741,721 - Black , et al. June 22, 2	2010-06-22
Soi Substrates And Soi Devices, And Methods For Forming The Same App 20100148259 - Dyer; Thomas W. ; et al.	2010-06-17
CMOS devices with hybrid channel orientations and method for fabricating the same Grant 7,736,966 - Dyer , et al. June 15, 2	2010-06-15
FinFET SRAM with asymmetric gate and method of manufacture thereof Grant 7,737,501 - Zhu , et al. June 15, 2	2010-06-15
CMOS diodes with dual gate conductors, and methods for forming the same Grant 7,737,500 - Onsongo , et al. June 15, 2	2010-06-15
High Aspect Ratio Electroplated Metal Feature And Method App 20100143649 - Edelstein; Daniel C. ; et al.	2010-06-10
Integration scheme for multiple metal gate work function structures Grant 7,732,872 - Cheng , et al. June 8, 2	2010-06-08
SRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function Grant 7,728,392 - Yang , et al. June 1, 2	2010-06-01
High aspect ratio electroplated metal feature and method Grant 7,727,890 - Edelstein , et al. June 1, 2	2010-06-01
Method And Structure For Forming Strained Si For Cmos Devices App 20100109048 - STEEGEN; An L. ; et al.	2010-05-06
Method to increase strain enhancement with spacerless FET and dual liner process Grant 7,709,317 - Yang , et al. May 4, 2	2010-05-04
Semiconductor Device Structure Having Enhanced Performance Fet Device App 20100096673 - Chen; Xiangdong ; et al.	2010-04-22
Method and structure for forming strained Si for CMOS devices Grant 7,700,951 - Steegen , et al. April 20, 2	2010-04-20
Dual damascene metal interconnect structure having a self-aligned via Grant 7,696,085 - Li , et al. April 13, 2	2010-04-13
Electrical fuse having sublithographic cavities thereupon Grant 7,675,137 - Kim , et al. March 9, 2	2010-03-09
SOI substrates and SOI devices, and methods for forming the same Grant 7,666,721 - Dyer , et al. February 23, 2	2010-02-23
Field Effect Device With Gate Electrode Edge Enhanced Gate Dielectric And Method For Fabrication App 20100038705 - Doris; Bruce B. ; et al.	2010-02-18
Method to enhance device performance with selective stress relief Grant 7,659,174 - Lee , et al. February 9, 2	2010-02-09
Semiconductor Device And Method Of Manufacturing App 20100019322 - Chen; Xiangdong ; et al.	2010-01-28
Electrical Fuse Having Sublithographic Cavities Thereupon App 20100005649 - Kim; Deok-kee ; et al.	2010-01-14
Cmos Devices Having Reduced Threshold Voltage Variations And Methods Of Manufacture Thereof App 20090315117 - Dyer; Thomas W. ; et al.	2009-12-24
Structure and method to form improved isolation in a semiconductor device Grant 7,635,899 - Yang , et al. December 22, 2	2009-12-22
Semiconductor device structure having enhanced performance FET device Grant 7,635,620 - Chen , et al. December 22, 2	2009-12-22
Structure And Method To Integrate Dual Silicide With Dual Stress Liner To Improve Cmos Performance App 20090309164 - Chen; Xiangdong ; et al.	2009-12-17
Structure And Method To Form E-fuse With Enhanced Current Crowding App 20090309184 - Kim; Deok-kee ; et al.	2009-12-17
Carrier Mobility Enhanced Channel Devices And Method Of Manufacture App 20090302412 - CHENG; KANGGUO ; et al.	2009-12-10
Structure And Method To Form Dual Silicide E-fuse App 20090302417 - Kim; Deok-kee ; et al.	2009-12-10
FinFET with sublithographic fin width Grant 7,625,790 - Yang December 1, 2	2009-12-01
Finfet With A V-shaped Channel App 20090283829 - Dyer; Thomas W. ; et al.	2009-11-19
Overlapped stressed liners for improved contacts Grant 7,612,414 - Chen , et al. November 3, 2	2009-11-03
High Performance 3d Fet Structures, And Methods For Forming The Same Using Preferential Crystallographic Etching App 20090267196 - Dyer; Thomas W. ; et al.	2009-10-29
Complementary Field Effect Transistors Having Embedded Silicon Source And Drain Regions App 20090256173 - Chen; Xiangdong ; et al.	2009-10-15
Metal Gate Compatible Flash Memory Gate Stack App 20090256211 - Booth, Jr.; Roger A. ; et al.	2009-10-15
Semiconductor Devices Having Tensile And/or Compressive Stress And Methods Of Manufacturing App 20090230427 - DYER; THOMAS W. ; et al.	2009-09-17
Low Contact Resistance Metal Contact App 20090218695 - Wong; Keith Kwong Hon ; et al.	2009-09-03
Method And Structure For Relieving Transistor Performance Degradation Due To Shallow Trench Isolation Induced Stress App 20090206442 - Divakaruni; Ramachandra ; et al.	2009-08-20
Dual Damascene Metal Interconnect Structure Having A Self-aligned Via App 20090206489 - Li; Wai-kin ; et al.	2009-08-20
Multiwalled Carbon Nanotube Memory Device App 20090201743 - Yang; Haining S.	2009-08-13
Complementary transistors having different source and drain extension spacing controlled by different spacer sizes Grant 7,572,692 - Yang August 11, 2	2009-08-11
Semiconductor structure and method of manufacture Grant 7,569,446 - Doris , et al. August 4, 2	2009-08-04
High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching Grant 7,569,489 - Dyer , et al. August 4, 2	2009-08-04
Method of forming transistor structure having stressed regions of opposite types Grant 7,569,447 - Yang , et al. August 4, 2	2009-08-04
Low contact resistance metal contact Grant 7,566,651 - Wong , et al. July 28, 2	2009-07-28
High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching Grant 7,566,949 - Dyer , et al. July 28, 2	2009-07-28
Sram Device Structure Including Same Band Gap Transistors Having Gate Stacks With High-k Dielectrics And Same Work Function App 20090174010 - Yang; Haining S. ; et al.	2009-07-09
Reversible electric fuse and antifuse structures for semiconductor devices Grant 7,557,424 - Wong , et al. July 7, 2	2009-07-07
Method and structure for forming strained SI for CMOS devices Grant 7,550,338 - Steegen , et al. June 23, 2	2009-06-23
Dual Oxide Stress Liner App 20090152638 - BELYANSKY; MICHAEL P. ; et al.	2009-06-18
High Aspect Ratio Electroplated Metal Feature And Method App 20090148677 - Edelstein; Daniel C. ; et al.	2009-06-11
Patterning Method Using A Combination Of Photolithography And Copolymer Self-assemblying Lithography Techniques App 20090148795 - Li; Wai-Kin ; et al.	2009-06-11
Method and structure for forming strained devices Grant 7,545,004 - Yang , et al. June 9, 2	2009-06-09
High Performance Mosfet Comprising A Stressed Gate Metal Silicide Layer And Method Of Fabricating The Same App 20090134470 - Yang; Haining S.	2009-05-28
Electrical Fuse And Method Of Making App 20090115020 - YANG; Chih-Chao ; et al.	2009-05-07
CMOS gate conductor having cross-diffusion barrier Grant 7,528,451 - Zhu , et al. May 5, 2	2009-05-05
Finfet Memory Device With Dual Separate Gates And Method Of Operation App 20090108351 - Yang; Haining S. ; et al.	2009-04-30
Integration Scheme For Multiple Metal Gate Work Function Structures App 20090108356 - Cheng; Kangguo ; et al.	2009-04-30
Dual Workfunction Silicide Diode App 20090108364 - Yang; Haining S. ; et al.	2009-04-30
Electrical Fuse And Method Of Making App 20090098689 - YANG; Chih-Chao ; et al.	2009-04-16
Methods for forming CMOS devices with intrinsically stressed metal silicide layers Grant 7,504,336 - Purtell , et al. March 17, 2	2009-03-17
Methods And Systems Involving Electrically Programmable Fuses App 20090057818 - Kim; Deok-kee ; et al.	2009-03-05
Electrical fuse and method of making Grant 7,491,585 - Yang , et al. February 17, 2	2009-02-17
Electromigration Resistant Interconnect Structure App 20090039512 - Yang; Haining S. ; et al.	2009-02-12
Electrical Fuses And Resistors Having Sublithographic Dimensions App 20090032959 - Black; Charles T. ; et al.	2009-02-05
Semiconductor Transistors Having Reduced Distances Between Gate Electrode Regions App 20090032886 - Wong; Robert C. ; et al.	2009-02-05
Two-sided semiconductor-on-insulator structures and methods of manufacturing the same Grant 7,485,508 - Dyer , et al. February 3, 2	2009-02-03
Electrical Fuse Having Sublithographic Cavities Thereupon App 20090026574 - Kim; Deok-kee ; et al.	2009-01-29
Finfet With Sublithographic Fin Width App 20090026543 - Yang; Haining S.	2009-01-29
Hybrid Orientation Substrate And Method For Fabrication Thereof App 20090029531 - Yang; Haining S. ; et al.	2009-01-29
Partially Gated Finfet App 20090026523 - Wong; Robert C. ; et al.	2009-01-29
Multiwalled carbon nanotube memory device Grant 7,482,652 - Yang January 27, 2	2009-01-27
Hybrid orientation substrate and method for fabrication of thereof Grant 7,482,209 - Yang , et al. January 27, 2	2009-01-27
Electrical Fuse Having A Cavity Thereupon App 20090021338 - Kim; Deok-kee ; et al.	2009-01-22
Finfet Sram With Asymmetric Gate And Method Of Manufacture Thereof App 20090014798 - Zhu; Huilong ; et al.	2009-01-15
Methods Of Patterning Self-assembly Nano-structure And Forming Porous Dielectric App 20090001045 - Chen; Kuang-Jung ; et al.	2009-01-01
Dual Stress Liner Efuse App 20090001506 - Kim; Deok-Kee ; et al.	2009-01-01
Method Of Forming An Soi Substrate Contact App 20090001466 - Yang; Haining S. ; et al.	2009-01-01
High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same Grant 7,470,943 - Yang December 30, 2	2008-12-30
Electrical Fuse With Sublithographic Dimension App 20080308900 - Kim; Deok-kee ; et al.	2008-12-18
Semiconductor Structure And Method Of Manufacture App 20080311714 - Doris; Bruce B. ; et al.	2008-12-18
Method and apparatus for increase strain effect in a transistor channel Grant 7,462,915 - Yang , et al. December 9, 2	2008-12-09
Soi Mosfet With A Metal Semiconductor Alloy Gate-to-body Bridge App 20080290413 - Mandelman; Jack A. ; et al.	2008-11-27
CMOS devices with hybrid channel orientations and method for fabricating the same Grant 7,456,450 - Dyer , et al. November 25, 2	2008-11-25
Extended Depth Inter-well Isolation Structure App 20080283930 - Dyer; Thomas W. ; et al.	2008-11-20
Self-aligned And Extended Inter-well Isolation Structure App 20080283962 - Dyer; Thomas W. ; et al.	2008-11-20
Method And Structure For Forming Strained Si For Cmos Devices App 20080283824 - STEEGEN; An L. ; et al.	2008-11-20
Process for making FinFET device with body contact and buried oxide junction isolation Grant 7,452,758 - Dyer , et al. November 18, 2	2008-11-18
Dopant Diffusion Barrier Layer To Prevent Out Diffusion App 20080268634 - Yang; Haining S.	2008-10-30
STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETs App 20080251853 - Chen; Xiangdong ; et al.	2008-10-16
Structure And Method Of Making A Semiconductor Integrated Circuit Tolerant Of Mis-alignment Of A Metal Contact Pattern App 20080246093 - Yang; Haining S.	2008-10-09
Structure and method to optimize strain in CMOSFETs Grant 7,432,553 - Chen , et al. October 7, 2	2008-10-07
Cmos Gate Conductor Having Cross-diffusion Barrier App 20080237749 - Zhu; Huilong ; et al.	2008-10-02
SILICON ON INSULATOR (SOI) FIELD EFFECT TRANSISTORS (FETs) WITH ADJACENT BODY CONTACTS App 20080237708 - Mandelman; Jack A. ; et al.	2008-10-02
Low Contact Resistance Metal Contact App 20080237867 - Wong; Keith Kwong Hon ; et al.	2008-10-02
Metal Silicide Alloy Local Interconnect App 20080239792 - Wann; Clement H. ; et al.	2008-10-02
Overlapped Stressed Liners For Improved Contacts App 20080237737 - Chen; Xiangdong ; et al.	2008-10-02
Non-planar Fuse Structure Including Angular Bend And Method For Fabrication Thereof App 20080237786 - Yang; Haining S. ; et al.	2008-10-02
Method and structure for forming strained SI for CMOS devices Grant 7,429,752 - Steegen , et al. September 30, 2	2008-09-30
Structure Having Dual Silicide Region And Related Method App 20080230848 - Yang; Chih-Chao ; et al.	2008-09-25
Contact Structure Having Dielectric Spacer And Method App 20080230906 - Wong; Keith Kwong Hon ; et al.	2008-09-25
Process For Making Finfet Device With Body Contact And Buried Oxide Junction Isolation App 20080224213 - Dyer; Thomas W. ; et al.	2008-09-18
Method And Structure For Controlling Stress In A Transistor Channel App 20080217696 - YANG; Haining S. ; et al.	2008-09-11
Semiconductor Device Structure Having Enhanced Performance Fet Device App 20080217665 - Chen; Xiangdong ; et al.	2008-09-11
Soi Mosfet Device With Adjustable Threshold Voltage App 20080191788 - Chen; Xiangdong ; et al.	2008-08-14
Dual stress liner App 20080185657 - Chen; Xiangdong ; et al.	2008-08-07
Patterning sub-lithographic features with variable widths Grant 7,407,890 - Yang August 5, 2	2008-08-05
Two-sided Semiconductor-on-insulator Structures And Methods Of Manufacturing The Same App 20080179678 - Dyer; Thomas W. ; et al.	2008-07-31
Sub-lithographic Gate Length Transistor Using Self-assembling Polymers App 20080179667 - Yang; Haining S. ; et al.	2008-07-31
Sub-lithographic Interconnect Patterning Using Self-assembling Polymers App 20080182402 - Li; Wai-Kin ; et al.	2008-07-31
Structure And Method To Form Semiconductor-on-pores (sop) For High Device Performance And Low Manufacturing Cost App 20080179712 - de Souza; Joel P. ; et al.	2008-07-31
Hybrid Interconnect Structure For Performance Improvement And Reliability Enhancement App 20080174017 - Yang; Chih-Chao ; et al.	2008-07-24
Structure And Method To Form Improved Isolation In A Semiconductor Device App 20080171420 - Yang; Haining S. ; et al.	2008-07-17
Sub-lithographic Faceting For Mosfet Performance Enhancement App 20080169535 - Butt; Shahid A. ; et al.	2008-07-17
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 7,396,714 - Chen , et al. July 8, 2	2008-07-08
Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals Grant 7,396,724 - Chan , et al. July 8, 2	2008-07-08
Reversible Electric Fuse And Antifuse Structures For Semiconductor Devices App 20080157269 - Wong; Keith Kwong Hon ; et al.	2008-07-03
Nano-fuse Structural Arrangements Having Blow Protection Barrier Spaced From And Surrounding Fuse Link App 20080128771 - Yang; Haining S. ; et al.	2008-06-05
Structure And Method For Multiple Height Finfet Devices App 20080128797 - Dyer; Thomas W. ; et al.	2008-06-05
Method and structure for controlling stress in a transistor channel Grant 7,381,609 - Yang , et al. June 3, 2	2008-06-03
Fet Structure Using Disposable Spacer And Stress Inducing Layer App 20080124880 - Lin; Wenhe ; et al.	2008-05-29
Method Of Enhancing Hole Mobility App 20080116484 - Utomo; Henry K. ; et al.	2008-05-22
Dual Stress Liner App 20080116524 - Chen; Xiangdong ; et al.	2008-05-22
Hybrid Orientation Substrate And Method For Fabrication Thereof App 20080111214 - Yang; Haining S. ; et al.	2008-05-15
Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost Grant 7,365,399 - de Souza , et al. April 29, 2	2008-04-29
Electrical Fuse And Method Of Making App 20080093703 - Yang; Chih-Chao ; et al.	2008-04-24
Cmos Devices With Hybrid Channel Orientations And Method For Fabricating The Same App 20080096339 - Dyer; Thomas W. ; et al.	2008-04-24
Dual stress liner Grant 7,361,539 - Chen , et al. April 22, 2	2008-04-22
Structure And Method Of Forming Transistor Density Based Stress Layers In Cmos Devices App 20080087965 - Chen; Xiangdong ; et al.	2008-04-17
STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETs App 20080070357 - Chen; Xiangdong ; et al.	2008-03-20
Method To Enhance Device Performance With Selective Stress Relief App 20080050868 - Lee; Yong Meng ; et al.	2008-02-28
Heterojunction Tunneling Field Effect Transistors, And Methods For Fabricating The Same App 20080050881 - Chen; Xiangdong ; et al.	2008-02-28
Method And Structure To Use An Etch Resistant Liner On Transistor Gate Structure To Achieve High Device Performance App 20080036017 - Ng; Hung Y. ; et al.	2008-02-14
BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT App 20080023752 - Chen; Xiangdong ; et al.	2008-01-31
Structure and method to implement dual stressor layers with improved silicide control App 20080026523 - Lee; Yong Meng ; et al.	2008-01-31
Improved Cmos Devices With Stressed Channel Regions, And Methods For Fabricating The Same App 20080001182 - Chen; Xiangdong ; et al.	2008-01-03
Method And Structure For Forming Strained Si For Cmos Devices App 20080003735 - STEEGEN; An L. ; et al.	2008-01-03
High Performance 3d Fet Structures, And Methods For Forming The Same Using Preferential Crystallographic Etching App 20070298552 - Dyer; Thomas W. ; et al.	2007-12-27
Method to enhance device performance with selective stress relief Grant 7,309,637 - Lee , et al. December 18, 2	2007-12-18
Structure to use an etch resistant liner on transistor gate structure to achieve high device performance Grant 7,307,323 - Ng , et al. December 11, 2	2007-12-11
Method To Enhance Cmos Transistor Performance By Inducing Strain In The Gate And Channel App 20070275522 - Yang; Haining S.	2007-11-29
Dual Stress Liner App 20070269942 - Chen; Xiangdong ; et al.	2007-11-22
Structure And Method For Forming Cmos Devices With Intrinsically Stressed Silicide Using Silicon Nitride Cap App 20070269970 - Purtell; Robert J. ; et al.	2007-11-22
Method of making strained channel CMOS transistors having lattice-mismatched epitaxial Grant 7,297,583 - Chen , et al. November 20, 2	2007-11-20
Method of forming transistor structure having stressed regions of opposite types App 20070259489 - Yang; Haining S. ; et al.	2007-11-08
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 7,291,528 - Chen , et al. November 6, 2	2007-11-06
Improved Cmos Diodes With Dual Gate Conductors, And Methods For Forming The Same App 20070252212 - Onsongo; David M. ; et al.	2007-11-01
High Performance 3d Fet Structures, And Methods For Forming The Same Using Preferential Crystallographic Etching App 20070254412 - Dyer; Thomas W. ; et al.	2007-11-01
Patterning Sub-lithographic Features With Variable Widths App 20070249174 - Yang; Haining S.	2007-10-25
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions App 20070249114 - Chen; Huajie ; et al.	2007-10-25
Method of fabricating strained channel field effect transistor pair having underlapped dual liners Grant 7,285,488 - Yang October 23, 2	2007-10-23
Structures And Methods For Forming Sram Cells With Self-aligned Contacts App 20070241411 - Yang; Haining S. ; et al.	2007-10-18
Method of forming contact for dual liner product Grant 7,282,435 - Yang , et al. October 16, 2	2007-10-16
Improved Soi Substrates And Soi Devices, And Methods For Forming The Same App 20070218603 - Dyer; Thomas W. ; et al.	2007-09-20
Transistor structure having stressed regions of opposite types underlying channel and source/drain regions Grant 7,271,442 - Yang , et al. September 18, 2	2007-09-18
Structure And Method To Induce Strain In A Semiconductor Device Channel With Stressed Film Under The Gate App 20070187773 - YANG; Haining S. ; et al.	2007-08-16
Structure and method to induce strain in a semiconductor device channel with stressed film under the gate Grant 7,256,081 - Yang , et al. August 14, 2	2007-08-14
Cmos Devices With Hybrid Channel Orientations And Method For Fabricating The Same App 20070181980 - Dyer; Thomas W. ; et al.	2007-08-09
Heterojunction Tunneling Field Effect Transistors, And Methods For Fabricating The Same App 20070178650 - Chen; Xiangdong ; et al.	2007-08-02
Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost App 20070164358 - de Souza; Joel P. ; et al.	2007-07-19
Method to enhance device performance with selective stress relief App 20070134870 - Lee; Yong Meng ; et al.	2007-06-14
Structure And Method To Increase Strain Enhancement With Spacerless Fet And Dual Liner Process App 20070108525 - Yang; Haining S. ; et al.	2007-05-17
Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern Grant 7,217,647 - Yang May 15, 2	2007-05-15
Integrated Circuits Having Strained Channel Field Effect Transistors And Methods Of Making App 20070099360 - Lee; Yong Meng ; et al.	2007-05-03
High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same App 20070040225 - Yang; Haining S.	2007-02-22
Method And Structure For Forming Strained Si For Cmos Devices App 20070020806 - STEEGAN; An L. ; et al.	2007-01-25
Method And Apparatus For Increase Strain Effect In A Transistor Channel App 20060281272 - YANG; Haining S. ; et al.	2006-12-14
Method of forming contact for dual liner product App 20060261477 - Yang; Haining S. ; et al.	2006-11-23
Method of fabricating strained channel field effect transistor pair having underlapped dual liners App 20060261480 - Yang; Haining S.	2006-11-23
Method and structure for forming strained Si for CMOS devices Grant 7,129,126 - Steegen , et al. October 31, 2	2006-10-31
Dual-hybrid Liner Formation Without Exposing Silicide Layer To Photoresist Stripping Chemicals App 20060228848 - Chan; Victor ; et al.	2006-10-12
Method And Structure For Forming Strained Devices App 20060228836 - Yang; Haining S. ; et al.	2006-10-12
Method and apparatus to increase strain effect in a transistor channel Grant 7,118,999 - Yang , et al. October 10, 2	2006-10-10
Structure for strained channel field effect transistor pair having underlapped dual liners Grant 7,102,233 - Yang September 5, 2	2006-09-05
Structure for strained channel field effect transistor pair having a member and a contact via Grant 7,098,536 - Yang , et al. August 29, 2	2006-08-29
Stucture And Method To Induce Strain In A Semiconductor Device Channel With Stressed Film Under The Gate App 20060172500 - Yang; Haining S. ; et al.	2006-08-03
Structure And Method To Optimize Strain In Cmosfets App 20060157795 - Chen; Xiangdong ; et al.	2006-07-20
Structure And Method To Enhance Stress In A Channel Of Cmos Devices Using A Thin Gate App 20060160317 - Zhu; Huilong ; et al.	2006-07-20
Transistor Structure Having Stressed Regions Of Opposite Types Underlying Channel And Source/drain Regions App 20060151833 - Yang; Haining S. ; et al.	2006-07-13
Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance App 20060145275 - Ng; Hung Y. ; et al.	2006-07-06
Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance Grant 7,064,027 - Ng , et al. June 20, 2	2006-06-20
Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern App 20060118829 - Yang; Haining S.	2006-06-08
Contact For Dual Liner Product App 20060099793 - Yang; Haining S. ; et al.	2006-05-11
Structure And Method Of Making A Semiconductor Integrated Circuit Tolerant Of Mis-alignment Of A Metal Contact Pattern App 20060099729 - Yang; Haining S.	2006-05-11
Method To Enhance Cmos Transistor Performance By Inducing Strain In The Gate And Channel App 20060099765 - Yang; Haining S.	2006-05-11
Structure And Method For Strained Channel Field Effect Transistor Pair Having Underlapped Dual Liners App 20060097315 - Yang; Haining S.	2006-05-11
MOSFET structure with high mechanical stress in the channel Grant 7,002,209 - Chen , et al. February 21, 2	2006-02-21
Structure and method to improve SRAM stability without increasing cell area or off current Grant 6,984,564 - Huang , et al. January 10, 2	2006-01-10
Structure And Method To Improve Sram Stability Without Increasing Cell Area Or Off Current App 20050285202 - Huang, Shih-Fen ; et al.	2005-12-29
Complementary transistors having different source and drain extension spacing controlled by different spacer sizes App 20050263826 - Yang, Haining S.	2005-12-01
MOSFET structure with high mechanical stress in the channel App 20050260808 - Chen, Xiangdong ; et al.	2005-11-24
Strained silicon NMOS devices with embedded source/drain App 20050242340 - Chidambarrao, Dureseti ; et al.	2005-11-03
Complementary transistors having different source and drain extension spacing controlled by different spacer sizes Grant 6,946,709 - Yang September 20, 2	2005-09-20
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions App 20050158931 - Chen, Huajie ; et al.	2005-07-21
Method And Apparatus To Increase Strain Effect In A Transistor Channel App 20050158955 - Yang, Haining S. ; et al.	2005-07-21
Method And Structure For Controlling Stress In A Transistor Channel App 20050158937 - Yang, Haining S. ; et al.	2005-07-21
Method of making strained channel CMOS transistors having lattice-mismatched epitaxial App 20050148133 - Chen, Huaje ; et al.	2005-07-07
Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions Grant 6,906,360 - Chen , et al. June 14, 2	2005-06-14
Complementary transistors having different source and drain extension spacing controlled by different spacer sizes App 20050116296 - Yang, Haining S.	2005-06-02
Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance App 20050104095 - Ng, Hung Y. ; et al.	2005-05-19
Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 6,891,192 - Chen , et al. May 10, 2	2005-05-10
METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES App 20050093076 - Steegen, An L. ; et al.	2005-05-05
Strained silicon NMOS devices with embedded source/drain Grant 6,881,635 - Chidambarrao , et al. April 19, 2	2005-04-19
Structure And Method Of Making Strained Channel Cmos Transistors Having Lattice-mismatched Epitaxial Extension And Source And Drain Regions App 20050051851 - Chen, Huajie ; et al.	2005-03-10
Structure And Method Of Making Strained Semiconductor Cmos Transistors Having Lattice-mismatched Source And Drain Regions App 20050029601 - Chen, Huajie ; et al.	2005-02-10