Yang; Fuji

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Fuji.The latest application filed is for "methods and apparatus for improved phase linearity in a multi-phase based clock/timing recovery system".

Company Profile

0.13.11

Yang; Fuji - Holmdel Monmouth County
Yang; Fuji - Old Bridge NJ
Yang; Fuji - Old Bridg NJ
Yang; Fuji - Monmouth NJ
Yang; Fuji - Clichy FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and apparatus for improved phase linearity in a multi-phase based clock/timing recovery system Grant 7,808,329 - Azadet , et al. October 5, 2	2010-10-05
Duty cycle correction circuit for high-speed clock signals Grant 7,733,143 - Guo , et al. June 8, 2	2010-06-08
Methods And Apparatus For Improved Phase Linearity In A Multi-Phase Based Clock/Timing Recovery System App 20100034333 - Azadet; Kameran ; et al.	2010-02-11
Multiple frequency generator for quadrature amplitude modulated communications Grant 7,598,815 - Chen , et al. October 6, 2	2009-10-06
Digital phase-looked loop Grant 7,577,225 - Azadet , et al. August 18, 2	2009-08-18
Duty Cycle Correction Circuit For High-speed Clock Signals App 20090160516 - Guo; Chunbing ; et al.	2009-06-25
Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof Grant 7,426,247 - Yang , et al. September 16, 2	2008-09-16
Multiple Frequency Generator For Quadrature Amplitude Modulated Communications App 20080100387 - Chen; Jinghong ; et al.	2008-05-01
Common-mode shifting circuit for CML buffers Grant 7,355,451 - Azadet , et al. April 8, 2	2008-04-08
Method and apparatus for receiver detection on a PCI-Express bus Grant 7,222,290 - Guo , et al. May 22, 2	2007-05-22
Multi-channel Serdes Receiver For Chip-to-chip And Backplane Interconnects And Method Of Operation Thereof App 20070092039 - Yang; Fuji ; et al.	2007-04-26
Digital phase-locked loop App 20070025490 - Azadet; Kameran ; et al.	2007-02-01
Programmable receive-side channel equalizer Grant 7,164,711 - Yang , et al. January 16, 2	2007-01-16
Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof Grant 7,158,587 - Yang , et al. January 2, 2	2007-01-02
Multi-level pulse amplitude modulation receiver Grant 7,099,400 - Yang , et al. August 29, 2	2006-08-29
Common-mode shifting circuit for CML buffers App 20060017468 - Azadet; Kameran ; et al.	2006-01-26
Method and apparatus for receiver detection on a PCI-Express bus App 20050104623 - Guo, Chunbing ; et al.	2005-05-19
Programmable receive-side channel equalizer App 20040141552 - Yang, Fuji ; et al.	2004-07-22
Multi-level pulse amplitude modulation receiver App 20040141567 - Yang, Fuji ; et al.	2004-07-22
Four quadrant analog mixer-based delay-locked loop for clock and data recovery Grant 6,586,977 - Yang , et al. July 1, 2	2003-07-01
Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof App 20030053565 - Yang, Fuji ; et al.	2003-03-20
Four quadrant analog mixer-based delay-locked loop for clock and data recovery App 20020097073 - Yang, Fuji ; et al.	2002-07-25
Electronic digital-to-analog converter circuit for a baseband transmission system Grant 6,323,795 - Yang , et al. November 27, 2	2001-11-27
Low-noise current pulse generator device Grant 6,236,252 - Genest , et al. May 22, 2	2001-05-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.