Yang; Fu-Liang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Fu-Liang.The latest application filed is for "high efficiency external counter pulsation system and method of treatment using the system".

Company Profile

1.156.148

Yang; Fu-Liang - Hsinchu City TW
Yang; Fu-Liang - Hsinchu TW
Yang; Fu-Liang - Hsin-Chu TW
Yang; Fu-Liang - Hsin-Chu City TW
Yang; Fu-Liang - Taichung TW
YANG; Fu-Liang - Taichung City TW
Yang; Fu-Liang - Taipei N/A TW
Yang; Fu-Liang - Tainan TW
Yang; Fu-Liang - Tai Nan TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High Efficiency External Counter Pulsation System And Method of Treatment Using the System App 20210259909 - Yang; Fu-Liang ; et al.	2021-08-26
Diode array for connecting to phase change memory and method forming same Grant 10,861,700 - Lai , et al. December 8, 2	2020-12-08
Phase Change Memory with Diodes Embedded in Substrate App 20190051528 - Lai; Fang-Shi Jordan ; et al.	2019-02-14
Phase change memory with diodes embedded in substrate Grant 10,103,024 - Lai , et al. October 16, 2	2018-10-16
FinFET device for device characterization Grant 9,960,274 - Chen , et al. May 1, 2	2018-05-01
CMOS device with raised source and drain regions Grant 9,905,474 - Liang , et al. February 27, 2	2018-02-27
FinFET Device For Device Characterization App 20170018641 - Chen; Hao-Yu ; et al.	2017-01-19
Bio-chip and method for separating and concentrating particles using the same Grant 9,498,784 - Cheng , et al. November 22, 2	2016-11-22
FinFET for device characterization Grant 9,455,348 - Chen , et al. September 27, 2	2016-09-27
Phase Change Memory with Diodes Embedded in Substrate App 20160181106 - Lai; Fang-Shi Jordan ; et al.	2016-06-23
Phase change memory with diodes embedded in substrate Grant 9,276,209 - Lai , et al. March 1, 2	2016-03-01
Methods of forming phase change memory with various grain sizes Grant 9,190,610 - Liang , et al. November 17, 2	2015-11-17
Method of fabricating a resistive non-volatile memory device Grant 9,112,144 - Lee , et al. August 18, 2	2015-08-18
Key mechanism for a saxophone Grant 9,058,793 - Yang June 16, 2	2015-06-16
Key Mechanism For A Saxophone App 20150161972 - YANG; Fu-Liang	2015-06-11
STRUCTURE OF FinFETs App 20150145068 - CHEN; MIN-CHENG ; et al.	2015-05-28
Fully depleted SOI multiple threshold voltage application Grant 8,865,539 - Chen , et al. October 21, 2	2014-10-21
Structure for a multiple-gate FET device and a method for its fabrication Grant RE45,180 - Chen , et al. October 7, 2	2014-10-07
Structure for a multiple-gate FET device and a method for its fabrication Grant RE45,165 - Chen , et al. September 30, 2	2014-09-30
Programming optical device Grant 8,847,253 - Huang , et al. September 30, 2	2014-09-30
Strained gate electrodes in semiconductor devices Grant 8,835,291 - Huang , et al. September 16, 2	2014-09-16
Doping of semiconductor fin devices Grant 8,790,970 - Yeo , et al. July 29, 2	2014-07-29
Phase Change Memory with Various Grain Sizes App 20140110656 - Liang; Chun-Sheng ; et al.	2014-04-24
Bio-chip And Method For Separating And Concentrating Particles Using The Same App 20140083855 - Cheng; I-Fang ; et al.	2014-03-27
Method for fabricating patterned layer Grant 8,679,728 - Huang , et al. March 25, 2	2014-03-25
Semiconductor Structure And Method Of Fabricating The Same App 20140008726 - HSIAO; Yu-Jen ; et al.	2014-01-09
Method For Fabricating Metal Line And Device With Metal Line App 20140008799 - Jong; Chao-An ; et al.	2014-01-09
Phase change memory with various grain sizes Grant 8,618,524 - Liang , et al. December 31, 2	2013-12-31
Method for making dual silicide and germanide semiconductors Grant 8,603,882 - Chen , et al. December 10, 2	2013-12-10
Strained silicon device Grant 8,569,845 - Huang , et al. October 29, 2	2013-10-29
Relaxed silicon germanium substrate with low defect density Grant 8,564,018 - Lin , et al. October 22, 2	2013-10-22
Method For Fabricating Patterned Layer App 20130084530 - HUANG; Chien-Chao ; et al.	2013-04-04
Method for dicing semiconductor wafers Grant 8,288,842 - Lee , et al. October 16, 2	2012-10-16
Method For Making Dual Silicide And Germanide Semiconductors App 20120190163 - Chen; Szu-Hung ; et al.	2012-07-26
Method Of Fabricating A Resistive Non-volatile Memory Device App 20120178210 - Lee; Tzyh-Cheang ; et al.	2012-07-12
Integrated circuit structures with multiple FinFETs Grant 8,174,073 - Lee , et al. May 8, 2	2012-05-08
Memory array with a selector connected to multiple resistive cells Grant 8,173,990 - Lee , et al. May 8, 2	2012-05-08
Resistive non-volatile memory device Grant 8,154,003 - Lee , et al. April 10, 2	2012-04-10
CMOS Device with Raised Source and Drain Regions App 20110298049 - Liang; Chun-Sheng ; et al.	2011-12-08
Doping of semiconductor fin devices Grant 8,053,839 - Yeo , et al. November 8, 2	2011-11-08
Inductor energy loss reduction techniques Grant 8,049,300 - Yeh , et al. November 1, 2	2011-11-01
Fully Depleted SOI Multiple Threshold Voltage Application App 20110212579 - Chen; Hao-Yu ; et al.	2011-09-01
CMOS device with raised source and drain regions Grant 8,008,157 - Liang , et al. August 30, 2	2011-08-30
Phase change memory Grant 7,989,920 - Lee , et al. August 2, 2	2011-08-02
Phase Change Memory with Various Grain Sizes App 20110140066 - Liang; Chun-Sheng ; et al.	2011-06-16
Multiple-gate transistor structure and method for fabricating Grant 7,948,037 - Chen , et al. May 24, 2	2011-05-24
Method for fabricating a body contact in a finfet structure and a device including the same Grant 7,943,986 - Yang , et al. May 17, 2	2011-05-17
Phase Change Memory with Diodes Embedded in Substrate App 20110092041 - Lai; Fang-Shi Jordan ; et al.	2011-04-21
Metal gate semiconductor device and manufacturing method Grant 7,923,759 - Huang , et al. April 12, 2	2011-04-12
Phase change memory with various grain sizes Grant 7,893,420 - Liang , et al. February 22, 2	2011-02-22
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors Grant 7,888,201 - Yeo , et al. February 15, 2	2011-02-15
Multiple-gate transistors formed on bulk substrates Grant 7,863,674 - Yeo , et al. January 4, 2	2011-01-04
Methods and structures for planar and multiple-gate transistors formed on SOI Grant 7,851,276 - Yang , et al. December 14, 2	2010-12-14
Lithographic Machine Platform And Applications Thereof App 20100233437 - HUANG; Chien-Chao ; et al.	2010-09-16
Multiple-gate Transistor Structure And Method For Fabricating App 20100200923 - Chen; Hao-Yu ; et al.	2010-08-12
Doping of Semiconductor Fin Devices App 20100176424 - Yeo; Yee-Chia ; et al.	2010-07-15
Phase Change Memory App 20100140580 - Lee; Tzyh-Cheang ; et al.	2010-06-10
Sidewall memory with self-aligned asymmetrical source and drain configuration Grant 7,732,310 - Lee , et al. June 8, 2	2010-06-08
Multiple-gate transistor structure Grant 7,728,360 - Chen , et al. June 1, 2	2010-06-01
Memory Array with a Selector Connected to Multiple Resistive Cells App 20100117045 - Lee; Tzyh-Cheang ; et al.	2010-05-13
Silicon-on-insulator chip with multiple crystal orientations Grant 7,704,809 - Yeo , et al. April 27, 2	2010-04-27
Phase change memory Grant 7,705,424 - Lee , et al. April 27, 2	2010-04-27
Doping of semiconductor fin devices Grant 7,701,008 - Yeo , et al. April 20, 2	2010-04-20
Memory array with a selector connected to multiple resistive cells Grant 7,663,134 - Lee , et al. February 16, 2	2010-02-16
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer Grant 7,659,587 - Yeo , et al. February 9, 2	2010-02-09
Phase change memory cell with roundless micro-trenches Grant 7,642,170 - Lee , et al. January 5, 2	2010-01-05
Method for forming SOI device Grant 7,638,376 - Wen , et al. December 29, 2	2009-12-29
Gate electrode for a semiconductor fin device Grant 7,635,632 - Yeo , et al. December 22, 2	2009-12-22
Semiconductor flash device Grant 7,602,006 - Huang , et al. October 13, 2	2009-10-13
Phase Change Memory Device App 20090230375 - Liang; Chun-Sheng ; et al.	2009-09-17
SONOS type two-bit FinFET flash memory cell Grant 7,589,387 - Hwang , et al. September 15, 2	2009-09-15
Semiconductor-on-insulator (SOI) strained active area transistor Grant 7,585,711 - Chen , et al. September 8, 2	2009-09-08
High performance device design Grant 7,582,947 - Huang , et al. September 1, 2	2009-09-01
Strained Gate Electrodes in Semiconductor Devices App 20090203202 - Huang; Chien-Chao ; et al.	2009-08-13
Memory cells with improved program/erase windows Grant 7,573,095 - Lee , et al. August 11, 2	2009-08-11
CMOS devices with graded silicide regions Grant 7,545,006 - Chen , et al. June 9, 2	2009-06-09
Phase Change Memory with Diodes Embedded in Substrate App 20090108249 - Lai; Fang-Shi Jordan ; et al.	2009-04-30
Phase change memory cell with roundless micro-trenches App 20090087945 - Lee; Tzyh Cheang ; et al.	2009-04-02
Phase Change Memory with Various Grain Sizes App 20090078924 - Liang; Chun-Sheng ; et al.	2009-03-26
Resistive Non-volatile Memory Device App 20090039332 - Lee; Tzyh-Cheang ; et al.	2009-02-12
Semiconductor-on-insulator (SOI) strained active areas Grant 7,485,929 - Chen , et al. February 3, 2	2009-02-03
Structure and method for a sidewall SONOS memory device Grant 7,482,236 - Lee , et al. January 27, 2	2009-01-27
Manufacturing of memory array and periphery Grant 7,482,231 - Lee , et al. January 27, 2	2009-01-27
Memory Array with a Selector Connected to Multiple Resistive Cells App 20090014836 - Lee; Tzyh-Cheang ; et al.	2009-01-15
Method for forming semiconductor device with modified channel compressive stress Grant 7,462,554 - Huang , et al. December 9, 2	2008-12-09
Integrated circuit structures with multiple FinFETs App 20080296702 - Lee; Tsung-Lin ; et al.	2008-12-04
Phase Change Memory App 20080285328 - Lee; Tzyh-Cheang ; et al.	2008-11-20
Semiconductor nano-wire devices and methods of fabrication Grant 7,452,778 - Chen , et al. November 18, 2	2008-11-18
Fully Depleted SOI Multiple Threshold Voltage Application App 20080237717 - Chen; Hao-Yu ; et al.	2008-10-02
Recessed channel field effect transistor (FET) device Grant 7,429,769 - Diaz , et al. September 30, 2	2008-09-30
Semiconductor device with raised segment Grant 7,423,323 - Chen , et al. September 9, 2	2008-09-09
FinFET for device characterization App 20080185650 - Chen; Hao-Yu ; et al.	2008-08-07
Structure and method for a sidewall SONOS memory device Grant 7,405,119 - Lee , et al. July 29, 2	2008-07-29
Method for forming SOI device App 20080171419 - Wen; Cheng-Kuo ; et al.	2008-07-17
Silicon-on-Insulator Chip with Multiple Crystal Orientations App 20080160727 - Yeo; Yee-Chia ; et al.	2008-07-03
Relaxed Silicon Germanium Substrate With Low Defect Density App 20080142842 - LIN; Chun Chich ; et al.	2008-06-19
Programming Optical Device App 20080142830 - Huang; Chien-Chao ; et al.	2008-06-19
Memory cells with improved program/erase windows App 20080128791 - Lee; Tzyh-Cheang ; et al.	2008-06-05
Sidewall memory with self-aligned asymmetrical source and drain configuration App 20080132015 - Lee; Tzyh-Cheang ; et al.	2008-06-05
Fully depleted SOI multiple threshold voltage application Grant 7,382,023 - Chen , et al. June 3, 2	2008-06-03
Structure for a multiple-gate FET device and a method for its fabrication Grant 7,381,649 - Chen , et al. June 3, 2	2008-06-03
Silicon-on-insulator chip with multiple crystal orientations Grant 7,368,334 - Yeo , et al. May 6, 2	2008-05-06
CMOS device with raised source and drain regions App 20080102573 - Liang; Chun-Sheng ; et al.	2008-05-01
Programming optical device Grant 7,361,541 - Huang , et al. April 22, 2	2008-04-22
Relaxed silicon germanium substrate with low defect density Grant 7,357,838 - Lin , et al. April 15, 2	2008-04-15
Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof Grant 7,355,236 - Lee , et al. April 8, 2	2008-04-08
Strained silicon MOS devices Grant 7,342,289 - Huang , et al. March 11, 2	2008-03-11
Semiconductor-on-insulator (SOI) strained active area transistor App 20080029815 - Chen; Hao-Yu ; et al.	2008-02-07
CMOS devices with graded silicide regions App 20080029831 - Chen; Hung-Ming ; et al.	2008-02-07
Semiconductor-on-insulator chip with<100>-oriented transistors Grant 7,319,258 - Yang , et al. January 15, 2	2008-01-15
Structure for a non-volatile memory device App 20070291526 - Lee; Tzyh-Cheang ; et al.	2007-12-20
Spacer engineering on CMOS devices App 20070278541 - Huang; Chien-Chao ; et al.	2007-12-06
FinFET transistor device on SOI and method of fabrication Grant 7,300,837 - Chen , et al. November 27, 2	2007-11-27
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors Grant 7,301,206 - Yeo , et al. November 27, 2	2007-11-27
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors App 20070264762 - Yeo; Yee-Chia ; et al.	2007-11-15
Inductor Energy Loss Reduction Techniques App 20070246798 - Yeh; Andrew ; et al.	2007-10-25
Method for Fabricating a Body Contact in a Finfet Structure and a Device Including the Same App 20070228372 - Yang; Kuo-Nan ; et al.	2007-10-04
Structure and method for forming the gate electrode in a multiple-gate transistor Grant 7,276,763 - Yeo , et al. October 2, 2	2007-10-02
Stress intermedium engineering App 20070222035 - Huang; Chien-Chao ; et al.	2007-09-27
Structure and method for a sidewall SONOS memory device App 20070212841 - Lee; Tzyh-Cheang ; et al.	2007-09-13
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors Grant 7,268,024 - Yeo , et al. September 11, 2	2007-09-11
Complementary Metal Oxide Semiconductor Transistor Technology Using Selective Epitaxy of a Strained Silicon Germanium Layer App 20070205468 - Yeo; Yee-Chia ; et al.	2007-09-06
Contacts to semiconductor fin devices Grant 7,262,086 - Yeo , et al. August 28, 2	2007-08-28
Inductor energy loss reduction techniques Grant 7,247,922 - Yeh , et al. July 24, 2	2007-07-24
Method for fabricating a body contact in a Finfet structure and a device including the same Grant 7,244,640 - Yang , et al. July 17, 2	2007-07-17
Manufacturing of memory array and periphery App 20070161174 - Lee; Tzyh-Cheang ; et al.	2007-07-12
Structure and method for a sidewall SONOS memory device App 20070161195 - Lee; Tzyh-Cheang ; et al.	2007-07-12
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement Grant 7,238,989 - Yeo , et al. July 3, 2	2007-07-03
Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof App 20070145465 - Lee; Tzyh-Cheang ; et al.	2007-06-28
Methods and Structures for Planar and Multiple-Gate Transistors Formed on SOI App 20070134860 - Yang; Fu-Liang ; et al.	2007-06-14
Self-aligned double gate device and method for forming same Grant 7,230,270 - Chen , et al. June 12, 2	2007-06-12
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer Grant 7,226,832 - Yeo , et al. June 5, 2	2007-06-05
Method for dicing semiconductor wafers App 20070117352 - Lee; Hsin-Hui ; et al.	2007-05-24
Gate electrode for a semiconductor fin device App 20070111454 - Yeo; Yee-Chia ; et al.	2007-05-17
Strained gate electrodes in semiconductor devices App 20070108529 - Huang; Chien-Chao ; et al.	2007-05-17
Multiple-gate transistors formed on bulk substrates App 20070102763 - Yeo; Yee-Chia ; et al.	2007-05-10
CMOS inverters configured using multiple-gate transistors Grant 7,214,991 - Yeo , et al. May 8, 2	2007-05-08
Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory App 20070096200 - Lee; Tzyh-Cheang ; et al.	2007-05-03
CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof Grant 7,208,815 - Chen , et al. April 24, 2	2007-04-24
MOSFET device with a strained channel Grant 7,202,139 - Yeo , et al. April 10, 2	2007-04-10
Strained silicon device App 20070075356 - Huang; Chien-Chao ; et al.	2007-04-05
SONOS type two-bit FinFET flash memory cell App 20070076477 - Hwang; Jiunn-Ren ; et al.	2007-04-05
High performance device design App 20070075377 - Huang; Chien-Chao ; et al.	2007-04-05
Necked Finfet device App 20070063261 - CHEN; Haur-Ywh ; et al.	2007-03-22
High performance tunneling-biased MOSFET and a process for its manufacture Grant 7,187,000 - Yang , et al. March 6, 2	2007-03-06
Method for dicing semiconductor wafers Grant 7,183,137 - Lee , et al. February 27, 2	2007-02-27
Methods and structures for planar and multiple-gate transistors formed on SOI Grant 7,180,134 - Yang , et al. February 20, 2	2007-02-20
Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory Grant 7,176,084 - Lee , et al. February 13, 2	2007-02-13
Gate electrode for a semiconductor fin device Grant 7,176,092 - Yeo , et al. February 13, 2	2007-02-13
Self-aligned contact for silicon-on-insulator devices Grant 7,173,305 - Yang , et al. February 6, 2	2007-02-06
Multiple-gate transistors formed on bulk substrates Grant 7,172,943 - Yeo , et al. February 6, 2	2007-02-06
Programming optical device App 20070023755 - Huang; Chien-Chao ; et al.	2007-02-01
Field effect transistor (FET) device having corrugated structure and method for fabrication thereof Grant 7,170,118 - Yang January 30, 2	2007-01-30
Slim spacer device and manufacturing method Grant 7,164,189 - Huang , et al. January 16, 2	2007-01-16
Semiconductor-on-insulator (SOI) strained active areas App 20070010048 - Chen; Hao-Yu ; et al.	2007-01-11
DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area Grant 7,161,204 - Lin , et al. January 9, 2	2007-01-09
Self-aligned Conductive Spacer Process For Sidewall Control Gate Of High-speed Random Access Memory App 20060281254 - Lee; Tzyh-Cheang ; et al.	2006-12-14
Silicon-on-insulator ULSI devices with multiple silicon film thicknesses Grant 7,141,459 - Yang , et al. November 28, 2	2006-11-28
Strained silicon device manufacturing method Grant 7,135,372 - Huang , et al. November 14, 2	2006-11-14
Contacts to semiconductor fin devices App 20060244066 - Yeo; Yee-Chia ; et al.	2006-11-02
Semiconductor flash device App 20060237770 - Huang; Chien-Chao ; et al.	2006-10-26
Semiconductor-on-insulator (SOI) strained active areas Grant 7,125,759 - Chen , et al. October 24, 2	2006-10-24
Doping of semiconductor fin devices App 20060234431 - Yeo; Yee-Chia ; et al.	2006-10-19
Self-aligned contact for silicon-on-insulator devices App 20060234438 - Yang; Fu-Liang ; et al.	2006-10-19
Method of fabricating a necked FINFET device Grant 7,122,412 - Chen , et al. October 17, 2	2006-10-17
Doping of semiconductor fin devices App 20060220133 - Yeo; Yee-Chia ; et al.	2006-10-05
Semiconductor-on-insulator (soi) Strained Active Areas App 20060214232 - Chen; Hao-Yu ; et al.	2006-09-28
High performance tunneling-biased MOSFET and a process for its manufacture App 20060208316 - Yang; Kuo-Nan ; et al.	2006-09-21
Metal gate semiconductor device and manufacturing method App 20060202237 - Huang; Chien-Chao ; et al.	2006-09-14
Contacts to semiconductor fin devices Grant 7,105,894 - Yeo , et al. September 12, 2	2006-09-12
Semiconductor structure and method for integrating SOI devices and bulk devices Grant 7,105,897 - Chen , et al. September 12, 2	2006-09-12
Methods of forming semiconductor devices with high-k gate dielectric App 20060177997 - Lin; Chun-Chieh ; et al.	2006-08-10
Accumulation mode multiple gate transistor App 20060170053 - Yeo; Yee-Chia ; et al.	2006-08-03
ESD protection device App 20060157791 - Lee; Jian-Hsing ; et al.	2006-07-20
Doping of semiconductor fin devices Grant 7,074,656 - Yeo , et al. July 11, 2	2006-07-11
Substrate contact and method of forming the same Grant 7,053,453 - Tsao , et al. May 30, 2	2006-05-30
Self-aligned double gate device and method for forming same App 20060108644 - Chen; Hao-Yu ; et al.	2006-05-25
Semiconductor structure and method for integrating SOI devices and bulk devices App 20060097316 - Chen; Hao-Yu ; et al.	2006-05-11
Structure and method for forming the gate electrode in a multiple-gate transistor App 20060091428 - Yeo; Yee-Chia ; et al.	2006-05-04
Silicon-on-insulator chip with multiple crystal orientations App 20060084244 - Yeo; Yee-Chia ; et al.	2006-04-20
Method for fabricating a body contact in a finfet structure and a device including the same App 20060084211 - Yang; Kuo-Nan ; et al.	2006-04-20
Inductor energy loss reduction techniques App 20060065948 - Yeh; Andrew ; et al.	2006-03-30
CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof App 20060049460 - Chen; Hung-Wei ; et al.	2006-03-09
Strained silicon device manufacturing method App 20060051922 - Huang; Chien-Chao ; et al.	2006-03-09
Structure and method for forming the gate electrode in a multiple-gate transistor Grant 7,005,330 - Yeo , et al. February 28, 2	2006-02-28
Method for fabricating a recessed channel field effect transistor (FET) device App 20060033158 - Diaz; Carlos H. ; et al.	2006-02-16
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer App 20060008958 - Yeo; Yee-Chia ; et al.	2006-01-12
Method for forming semiconductor device with modified channel compressive stress App 20060003520 - Huang; Chien-Chao ; et al.	2006-01-05
SOI chip with mesa isolation and recess resistant regions Grant 6,979,867 - Yeo , et al. December 27, 2	2005-12-27
Semiconductor nano-wire devices and methods of fabrication App 20050275010 - Chen, Hung-Wei ; et al.	2005-12-15
Novel semiconductor device design App 20050275043 - Huang, Chien-Chao ; et al.	2005-12-15
Method for fabricating a recessed channel field effect transistor (FET) device Grant 6,974,730 - Diaz , et al. December 13, 2	2005-12-13
Semiconductor device with modified channel compressive stress Grant 6,975,006 - Huang , et al. December 13, 2	2005-12-13
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement App 20050272188 - Yeo, Yee-Chia ; et al.	2005-12-08
Method of fabricating a necked finfet device App 20050253193 - Chen, Haur-Ywh ; et al.	2005-11-17
Fully depleted SOI multiple threshold voltage application App 20050242398 - Chen, Hao-Yu ; et al.	2005-11-03
FinFET transistor device on SOI and method of fabrication App 20050242395 - Chen, Hau-Yu ; et al.	2005-11-03
Substrate contact and method of forming the same App 20050236712 - Tsao, Hsun-Chih ; et al.	2005-10-27
Method of manufacturing a microelectronic device with electrode perturbing sill App 20050230763 - Huang, Chien-Chao ; et al.	2005-10-20
Gate electrode for a semiconductor fin device App 20050233525 - Yeo, Yee-Chia ; et al.	2005-10-20
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement Grant 6,955,952 - Yeo , et al. October 18, 2	2005-10-18
Slim spacer device and manufacturing method App 20050224867 - Huang, Chien-Chao ; et al.	2005-10-13
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer Grant 6,953,972 - Yeo , et al. October 11, 2	2005-10-11
Metal gate semiconductor device and manufacturing method App 20050212015 - Huang, Chien-Chao ; et al.	2005-09-29
Method of forming DRAM capactiors with protected outside crown surface for more robust structures App 20050179076 - Lin, Chun-Chieh ; et al.	2005-08-18
Methods and structures for planar and multiple-gate transistors formed on SOI App 20050167750 - Yang, Fu-Liang ; et al.	2005-08-04
Relaxed silicon germanium substrate with low defect density App 20050158971 - Lin, Chun Chich ; et al.	2005-07-21
Semiconductor device with raised segment App 20050156248 - Chen, Hao-Yu ; et al.	2005-07-21
Method for fabricating a recessed channel filed effect transistor (FET) device App 20050133830 - Diaz, Carlos H. ; et al.	2005-06-23
Semiconductor chip with gate dielectrics for high-performance and low-leakage applications Grant 6,906,398 - Yeo , et al. June 14, 2	2005-06-14
Semiconductor nano-rod devices App 20050121706 - Chen, Hao-Yu ; et al.	2005-06-09
Silicon-on-insulator chip with multiple crystal orientations Grant 6,902,962 - Yeo , et al. June 7, 2	2005-06-07
Method for dicing semiconductor wafers App 20050118790 - Lee, Hsin-Hui ; et al.	2005-06-02
Complementary field-effect transistors and methods of manufacture App 20050116360 - Huang, Chien-Chao ; et al.	2005-06-02
SOI chip with mesa isolation and recess resistant regions App 20050101111 - Yeo, Yee-Chia ; et al.	2005-05-12
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors App 20050093067 - Yeo, Yee-Chia ; et al.	2005-05-05
Semiconductor-on-insulator chip with<100>-oriented transistors App 20050093105 - Yang, Fu-Liang ; et al.	2005-05-05
Relaxed silicon germanium substrate with low defect density Grant 6,878,610 - Lin , et al. April 12, 2	2005-04-12
Method of forming DRAM capacitors with protected outside crown surface for more robust structures Grant 6,875,655 - Lin , et al. April 5, 2	2005-04-05
Semiconductor device with raised segment Grant 6,872,606 - Chen , et al. March 29, 2	2005-03-29
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors Grant 6,867,433 - Yeo , et al. March 15, 2	2005-03-15
CMOS SRAM cell configured using multiple-gate transistors Grant 6,864,519 - Yeo , et al. March 8, 2	2005-03-08
SOI chip with mesa isolation and recess resistant regions Grant 6,864,149 - Yeo , et al. March 8, 2	2005-03-08
Semiconductor device with high-k gate dielectric App 20050035345 - Lin, Chun-Chieh ; et al.	2005-02-17
Multiple-gate transistors formed on bulk substrates App 20050035415 - Yeo, Yee-Chia ; et al.	2005-02-17
Semiconductor diode with reduced leakage App 20050035410 - Yeo, Yee-Chia ; et al.	2005-02-17
Strained-channel multiple-gate transistor Grant 6,855,990 - Yeo , et al. February 15, 2	2005-02-15
Semiconductor nano-rod devices Grant 6,855,606 - Chen , et al. February 15, 2	2005-02-15
Strained silicon MOS devices App 20050032321 - Huang, Chien-Chao ; et al.	2005-02-10
Field effect transistor (FET) device having corrugated structure and method for fabrication thereof App 20050023569 - Yang, Fu-Liang	2005-02-03
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors App 20050023633 - Yeo, Yee-Chia ; et al.	2005-02-03
Semiconductor device with modified channel compressive stress and the method for making same App 20050019998 - Huang, Chien-Chao ; et al.	2005-01-27
Multiple-gate transistors with improved gate control Grant 6,844,238 - Yeo , et al. January 18, 2	2005-01-18
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer App 20050009263 - Yeo, Yee-Chia ; et al.	2005-01-13
Mosfet device with a strained channel App 20050003599 - Yeo, Yee-Chia ; et al.	2005-01-06
Structure and method for forming the gate electrode in a multiple-gate transistor App 20040266077 - Yeo, Yee-Chia ; et al.	2004-12-30
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement App 20040266128 - Chen, Haur-Ywh ; et al.	2004-12-30
Semiconductor diodes with fin structure Grant 6,835,967 - Yeo , et al. December 28, 2	2004-12-28
SOI chip with mesa isolation and recess resistant regions App 20040222463 - Yeo, Yee-Chia ; et al.	2004-11-11
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors App 20040217420 - Yeo, Yee-Chia ; et al.	2004-11-04
Doping of semiconductor fin devices App 20040217433 - Yeo, Yee-Chia ; et al.	2004-11-04
Self-aligned contact for silicon-on-insulator devices App 20040203211 - Yang, Fu-Liang ; et al.	2004-10-14
Semiconductor device with raised segment App 20040197969 - Chen, Hao-Yu ; et al.	2004-10-07
Multiple-gate transistors with improved gate control App 20040198003 - Yeo, Yee-Chia ; et al.	2004-10-07
Silicon-on-insulator chip with multiple crystal orientations App 20040195646 - Yeo, Yee-Chia ; et al.	2004-10-07
Electrostatic discharge device protection structure Grant 6,800,516 - Chan , et al. October 5, 2	2004-10-05
Semiconductor diodes with fin structure App 20040188705 - Yeo, Yee-Chia ; et al.	2004-09-30
Method of forming dram capacitors with protected outside crown surface for more robust structures App 20040185613 - Lin, Chun-Chieh ; et al.	2004-09-23
Silicon-on-insulator ulsi devices with multiple silicon film thicknesses App 20040180478 - Yang, Fu-Liang ; et al.	2004-09-16
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement App 20040175872 - Yeo, Yee-Chia ; et al.	2004-09-09
Contacts to semiconductor fin devices App 20040169269 - Yeo, Yee-Chia ; et al.	2004-09-02
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement Grant 6,784,071 - Chen , et al. August 31, 2	2004-08-31
Semiconductor nano-rod devices App 20040166642 - Chen, Hao-Yu ; et al.	2004-08-26
BONDED SOI WAFER WITH <100> DEVICE LAYER AND <110> SUBSTRATE FOR PERFORMANCE IMPROVEMENT App 20040151917 - Chen, Haur-Ywh ; et al.	2004-08-05
Electrostatic discharge device protection structure App 20040140505 - Chan, Yi-Lang ; et al.	2004-07-22
Semiconductor chip with gate dielectrics for high-performance and low-leakage applications App 20040129995 - Yeo, Yee-Chia ; et al.	2004-07-08
CMOS inverters configured using multiple-gate transistors App 20040110331 - Yeo, Yee-Chia ; et al.	2004-06-10
Multiple-gate transistor structure and method for fabricating App 20040108523 - Chen, Hao-Yu ; et al.	2004-06-10
CMOS SRAM cell configured using multiple-gate transistors App 20040099885 - Yeo, Yee-Chia ; et al.	2004-05-27
Strained-channel multiple-gate transistor App 20040099903 - Yeo, Yee-Chia ; et al.	2004-05-27
Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices Grant 6,720,619 - Chen , et al. April 13, 2	2004-04-13
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer Grant 6,703,271 - Yeo , et al. March 9, 2	2004-03-09
Method of forming a self-aligned twin well structure with a single mask Grant 6,703,187 - Sheu , et al. March 9, 2	2004-03-09
Amorphizing ion implant local oxidation of silicon (LOCOS) method for forming an isolation region Grant 6,686,255 - Yang , et al. February 3, 2	2004-02-03
High performance PD SOI tunneling-biased MOSFET Grant 6,674,130 - Yang , et al. January 6, 2	2004-01-06
SOI MOSFET with compact body-tied-source structure App 20030222308 - Su, Ke-Wei ; et al.	2003-12-04
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer App 20030162348 - Yeo, Yee-Chia ; et al.	2003-08-28
Method of forming a self-aligned twin well structrue with a single mask App 20030129540 - Sheu, Yi-Ming ; et al.	2003-07-10
High performance PD SOI tunneling-biased mosfet App 20030122214 - Yang, Kuo-Nan ; et al.	2003-07-03
High performance PD SOI tunneling-biased MOSFET Grant 6,518,105 - Yang , et al. February 11, 2	2003-02-11
Amorphizing ion implant local oxidation of silicon (LOCOS) method for forming an isolation region App 20030022461 - Yang, Chi-Ming ; et al.	2003-01-30
Method of forming a transistor with a strained channel Grant 6,492,216 - Yeo , et al. December 10, 2	2002-12-10
Method of forming shallow trench isolation structure Grant 6,277,709 - Wang , et al. August 21, 2	2001-08-21
Method of fabricating a self-aligned contact Grant 6,248,643 - Hsieh , et al. June 19, 2	2001-06-19
Shallow trench isolator via non-critical chemical mechanical polishing Grant 6,171,929 - Yang , et al. January 9, 2	2001-01-09
Methods for shallow trench isolation Grant 6,159,821 - Cheng , et al. December 12, 2	2000-12-12
Self-planarized shallow trench isolation Grant 6,159,822 - Yang , et al. December 12, 2	2000-12-12
Method for simultaneously fabricating a DRAM capacitor and metal interconnections Grant 6,071,789 - Yang , et al. June 6, 2	2000-06-06
Method of making a shallow trench isolation for ULSI formation via in-direct CMP process Grant 6,057,210 - Yang , et al. May 2, 2	2000-05-02
Chemical mechanical polishing pad with controlled polish rate Grant 6,054,017 - Yang , et al. April 25, 2	2000-04-25
Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process Grant 6,037,216 - Liu , et al. March 14, 2	2000-03-14
Method for forming identifying characters on a silicon wafer Grant 6,037,259 - Lin , et al. March 14, 2	2000-03-14
Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device Grant 5,956,594 - Yang , et al. September 21, 1	1999-09-21
Method of forming multilevel interconnects in semiconductor devices Grant 5,854,130 - Yang , et al. December 29, 1	1998-12-29
Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode Grant 5,804,852 - Yang , et al. September 8, 1	1998-09-08
Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory Grant 5,792,689 - Yang , et al. August 11, 1	1998-08-11
Method of fabricating single crown, extendible to triple crown, stacked capacitor structures, using a self-aligned capacitor node contact Grant 5,677,227 - Yang , et al. October 14, 1	1997-10-14
Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures Grant 5,656,556 - Yang August 12, 1	1997-08-12

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