Yang; Chih-Yuh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yang; Chih-Yuh.The latest application filed is for "system and method for manufacturing self-aligned sti with single poly".

Company Profile

0.56.16

Yang; Chih-Yuh - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for manufacturing self-aligned STI with single poly Grant 10,622,370 - Thurgate , et al.	2020-04-14
System and method for manufacturing self-aligned STI with single poly Grant 9,276,007 - Thurgate , et al. March 1, 2	2016-03-01
Oro and orpro with bit line trench to suppress transport program disturb Grant 9,245,895 - Cheng , et al. January 26, 2	2016-01-26
System And Method For Manufacturing Self-aligned Sti With Single Poly App 20140312409 - Thurgate; Tim ; et al.	2014-10-23
Self-aligned STI with single poly for manufacturing a flash memory device Grant 8,642,441 - Thurgate , et al. February 4, 2	2014-02-04
Oro And Orpro With Bit Line Trench To Suppress Transport Program Disturb App 20110278660 - Cheng; Ning ; et al.	2011-11-17
ORO and ORPRO with bit line trench to suppress transport program disturb Grant 8,012,830 - Cheng , et al. September 6, 2	2011-09-06
SI trench between bitline HDP for BVDSS improvement Grant 7,951,675 - Xue , et al. May 31, 2	2011-05-31
Methods for forming small contacts Grant 7,915,160 - Tabery , et al. March 29, 2	2011-03-29
Methods for fabricating dual bit flash memory devices Grant 7,867,848 - Shen , et al. January 11, 2	2011-01-11
Methods For Fabricating Dual Bit Flash Memory Devices App 20100203694 - SHEN; Minghao ; et al.	2010-08-12
Methods for fabricating dual bit flash memory devices Grant 7,732,281 - Shen , et al. June 8, 2	2010-06-08
Methods for fabricating flash memory devices Grant 7,696,038 - Cheng , et al. April 13, 2	2010-04-13
Integrated circuit memory system employing silicon rich layers Grant 7,675,104 - Joshi , et al. March 9, 2	2010-03-09
Si Trench Between Bitline Hdp For Bvdss Improvement App 20090152669 - Xue; Lei ; et al.	2009-06-18
Oro And Orpro With Bit Line Trench To Suppress Transport Program Disturb App 20090039405 - Cheng; Ning ; et al.	2009-02-12
Integrated Circuit Memory System Employing Silicon Rich Layers App 20080023751 - Joshi; Amol Ramesh ; et al.	2008-01-31
Method for semiconductor gate line dimension reduction Grant 7,268,066 - Bonser , et al. September 11, 2	2007-09-11
Epitaxially grown fin for FinFET Grant 7,183,152 - Dakshina-Murthy , et al. February 27, 2	2007-02-27
Methods for forming small contacts Grant 7,183,223 - Tabery , et al. February 27, 2	2007-02-27
Method For Reducing Feature Line Edge Roughness App 20060154184 - Mahorowala; Arpan P. ; et al.	2006-07-13
Self aligned damascene gate Grant 7,029,958 - Tabery , et al. April 18, 2	2006-04-18
Source and drain protection and stringer-free gate formation in semiconductor devices Grant 7,029,959 - Yang , et al. April 18, 2	2006-04-18
Method for reducing resist height erosion in a gate etch process Grant 7,005,386 - Bell , et al. February 28, 2	2006-02-28
Semiconductor device having a gate structure surrounding a fin Grant 6,960,804 - Yang , et al. November 1, 2	2005-11-01
Method for patterning a feature using a trimmed hardmask Grant 6,913,958 - Plat , et al. July 5, 2	2005-07-05
Treatment of dielectric material to enhance etch rate Grant 6,905,971 - Tabery , et al. June 14, 2	2005-06-14
Self aligned damascene gate App 20050104091 - Tabery, Cyrus E. ; et al.	2005-05-19
CVD organic polymer film for advanced gate patterning Grant 6,864,556 - You , et al. March 8, 2	2005-03-08
Method for semiconductor gate line dimension reduction Grant 6,849,530 - Bonser , et al. February 1, 2	2005-02-01
Method for semiconductor gate line dimension reduction App 20050020019 - Bonser, Douglas J. ; et al.	2005-01-27
Epitaxially grown fin for FinFET Grant 6,835,618 - Dakshina-Murthy , et al. December 28, 2	2004-12-28
Enhanced transistor gate using E-beam radiation Grant 6,828,259 - Fisher , et al. December 7, 2	2004-12-07
Enhanced Transistor Gate Using E-beam Radiation App 20040209411 - Fisher, Philip A. ; et al.	2004-10-21
Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices Grant 6,797,552 - Chang , et al. September 28, 2	2004-09-28
Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal Grant 6,790,782 - Yang , et al. September 14, 2	2004-09-14
Method for forming a fin in a finFET device Grant 6,787,854 - Yang , et al. September 7, 2	2004-09-07
Etch stop layer for etching FinFET gate over a large topography Grant 6,787,476 - Dakshina-Murthy , et al. September 7, 2	2004-09-07
Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning Grant 6,773,998 - Fisher , et al. August 10, 2	2004-08-10
Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric Grant 6,764,966 - En , et al. July 20, 2	2004-07-20
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication Grant 6,764,949 - Bonser , et al. July 20, 2	2004-07-20
Method for reducing gate line deformation and reducing gate line widths in semiconductor devices Grant 6,764,947 - Chan , et al. July 20, 2	2004-07-20
Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance Grant 6,750,127 - Chang , et al. June 15, 2	2004-06-15
Ultra-thin resist shallow trench process using high selectivity nitride etch Grant 6,740,566 - Lyons , et al. May 25, 2	2004-05-25
Method for semiconductor gate line dimension reduction App 20040043590 - Bonser, Douglas J. ; et al.	2004-03-04
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication App 20040023475 - Bonser, Douglas J. ; et al.	2004-02-05
CVD silicon carbide layer as a BARC and hard mask for gate patterning Grant 6,653,735 - Yang , et al. November 25, 2	2003-11-25
Process for reducing the critical dimensions of integrated circuit device features Grant 6,653,231 - Okoroanyanwu , et al. November 25, 2	2003-11-25
Method for forming fins in a FinFET device using sacrificial carbon layer Grant 6,645,797 - Buynoski , et al. November 11, 2	2003-11-11
Process for forming sub-lithographic photoresist features by modification of the photoresist surface Grant 6,630,288 - Shields , et al. October 7, 2	2003-10-07
Analytical model for predicting the operating process window for lithographic patterning techniques based on photoresist trim technology Grant 6,606,738 - Bell , et al. August 12, 2	2003-08-12
Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer Grant 6,599,766 - Tabery , et al. July 29, 2	2003-07-29
Process for preventing deformation of patterned photoresist features Grant 6,589,709 - Okoroanyanwu , et al. July 8, 2	2003-07-08
Gate array with multiple dielectric properties and method for forming same Grant 6,563,183 - En , et al. May 13, 2	2003-05-13
Process for forming sub-lithographic photoresist features by modification of the photoresist surface App 20020160320 - Shields, Jeffrey A. ; et al.	2002-10-31
Process for reducing the critical dimensions of integrated circuit device features App 20020160628 - Okoroanyanwu, Uzodinma ; et al.	2002-10-31
Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual Grant 6,451,647 - Yang , et al. September 17, 2	2002-09-17
Ultra-thin Resist Shallow Trench Process Using Metal Hard Mask App 20010038972 - LYONS, CHRISTOPHER F. ; et al.	2001-11-08
Thin resist with nitride hard mask for gate etch application Grant 6,309,926 - Bell , et al. October 30, 2	2001-10-30
Ultra-thin Resist Shallow Trench Process Using High Selectivity Nitride Etch App 20010014512 - LYONS, CHRISTOPHER F. ; et al.	2001-08-16
Process for fabricating a semiconductor device component using a selective silicidation reaction Grant 6,211,044 - Xiang , et al. April 3, 2	2001-04-03
Method for shaping photoresist mask to improve high aspect ratio ion implantation Grant 6,200,884 - Yang , et al. March 13, 2	2001-03-13
Method using a thin resist mask for dual damascene stop layer etch Grant 6,184,128 - Wang , et al. February 6, 2	2001-02-06
Thin resist with amorphous silicon hard mask for via etch application Grant 6,165,695 - Yang , et al. December 26, 2	2000-12-26
Ultra-thin resist and silicon/oxide hard mask for metal etch Grant 6,156,658 - Wang , et al. December 5, 2	2000-12-05
Integrated circuit fabrication critical dimension control using self-limiting resist etch Grant 6,121,155 - Yang , et al. September 19, 2	2000-09-19
Controlled linewidth reduction during gate pattern formation using an SiON BARC Grant 6,107,172 - Yang , et al. August 22, 2	2000-08-22
Ultra-thin resist and nitride/oxide hard mask for metal etch Grant 6,020,269 - Wang , et al. February 1, 2	2000-02-01
Silicon oxime spacer for preventing over-etching during local interconnect formation Grant 5,990,524 - En , et al. November 23, 1	1999-11-23
Controlled linewidth reduction during gate pattern formation using a spin-on barc Grant 5,965,461 - Yang , et al. October 12, 1	1999-10-12

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