Yamase; Ryan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yamase; Ryan.The latest application filed is for "fabrication of through-silicon vias on silicon wafers".
- Yamase; Ryan - Santa Clara CA US
| Patent | Date |
|---|---|
| Silicon nitride passivation layer for covering high aspect ratio features Grant 8,563,095 - Rajagopalan , et al. October 22, 2 | 2013-10-22 |
| Fabrication of through-silicon vias on silicon wafers Grant 8,329,575 - Rajagopalan , et al. December 11, 2 | 2012-12-11 |
| Fabrication of through-silicon vias on silicon wafers Grant 8,283,237 - Rajagopalan , et al. October 9, 2 | 2012-10-09 |
| Fabrication Of Through-silicon Vias On Silicon Wafers App 20120164827 - RAJAGOPALAN; Nagarajan ; et al. | 2012-06-28 |
| Fabrication Of Through-silicon Vias On Silicon Wafers App 20120164829 - Rajagopalan; Nagarajan ; et al. | 2012-06-28 |
| Silicon Nitride Passivation Layer For Covering High Aspect Ratio Features App 20110223765 - RAJAGOPALAN; Nagarajan ; et al. | 2011-09-15 |
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