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Patent applications and USPTO patent grants for Yamamura; Masahiro.The latest application filed is for "method for forming catalyst layer for carbon nanostructure growth, liquid for catalyst layer formation, and process for...".
Patent | Date |
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Process for producing a carbon nanostructure Grant 9,309,123 - Nagasaka , et al. April 12, 2 | 2016-04-12 |
Method For Forming Catalyst Layer For Carbon Nanostructure Growth, Liquid For Catalyst Layer Formation, And Process For... App 20100291297 - Nagasaka; Takeshi ;   et al. | 2010-11-18 |
Semiconductor memory device Grant 6,864,559 - Nakazato , et al. March 8, 2 | 2005-03-08 |
Cathode ray tube with panel provided with colored layer Grant 6,856,082 - Suzuki , et al. February 15, 2 | 2005-02-15 |
Semiconductor memory device Grant 6,740,958 - Nakazato , et al. May 25, 2 | 2004-05-25 |
Method of treating surface of face panel for image display Grant 6,669,524 - Suzuki , et al. December 30, 2 | 2003-12-30 |
Semiconductor memory device App 20030178699 - Nakazato, Shinji ;   et al. | 2003-09-25 |
Semiconductor memory device App 20020153591 - Nakazato, Shinji ;   et al. | 2002-10-24 |
Method of treating surface of face panel used for image display device, and image display device comprising the treated face panel App 20020084742 - Yamamura, Masahiro ;   et al. | 2002-07-04 |
Cathode ray tube and method for manufacturing the same App 20020008460 - Suzuki, Atsushi ;   et al. | 2002-01-24 |
Method of treating surface of face panel for image display and image display App 20010028213 - Suzuki, Atsushi ;   et al. | 2001-10-11 |
Semiconductor memory device Grant 6,208,010 - Nakazato , et al. March 27, 2 | 2001-03-27 |
Semiconductor integrated circuit device, and process and apparatus for manufacturing the same Grant 5,910,010 - Nishizawa , et al. June 8, 1 | 1999-06-08 |
Signal transition detector circuit Grant 5,680,066 - Akioka , et al. October 21, 1 | 1997-10-21 |
Semiconductor device Grant 5,619,151 - Akioka , et al. April 8, 1 | 1997-04-08 |
Semiconductor memory device having separately biased wells for isolation Grant 5,497,023 - Nakazato , et al. March 5, 1 | 1996-03-05 |
Semiconductor CMOS memory device with separately biased wells Grant 5,386,135 - Nakazato , et al. January 31, 1 | 1995-01-31 |
Semiconductor memory device having bipolar transistor and structure to avoid soft error Grant 5,324,982 - Nakazato , et al. June 28, 1 | 1994-06-28 |
Semiconductor memory device Grant 5,148,255 - Nakazato , et al. September 15, 1 | 1992-09-15 |
Constant voltage output circuit Grant 4,283,674 - Kominami , et al. August 11, 1 | 1981-08-11 |
Protective circuit Grant 4,276,442 - Ienaka , et al. June 30, 1 | 1981-06-30 |
Differential amplification circuit Grant 4,264,873 - Kominami , et al. April 28, 1 | 1981-04-28 |
Differential amplifier Grant 4,059,808 - Sakamoto , et al. November 22, 1 | 1977-11-22 |
SEC | 0001513964 | YAMAMURA MASAHIRO |
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