Yamaguchi, Tadanori

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yamaguchi, Tadanori.The latest application filed is for "forming devices on a semiconductor substrate".

Company Profile

0.9.1

Yamaguchi, Tadanori - Portland OR
Yamaguchi; Tadanori - Hillsboro OR
Yamaguchi; Tadanori - Atsugi JA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Forming devices on a semiconductor substrate App 20020173092 - Yamaguchi, Tadanori ; et al.	2002-11-21
Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates Grant 6,303,413 - Kalnitsky , et al. October 16, 2	2001-10-16
Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls Grant 4,994,400 - Yamaguchi , et al. February 19, 1	1991-02-19
High speed double polycide bipolar/CMOS integrated circuit process Grant 4,902,640 - Sachitano , et al. February 20, 1	1990-02-20
Method for fabricating an isolation region in a semiconductor substrate Grant 4,876,214 - Yamaguchi , et al. October 24, 1	1989-10-24
Integrated circuit method Grant 4,486,266 - Yamaguchi December 4, 1	1984-12-04
Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas Grant 4,477,310 - Park , et al. October 16, 1	1984-10-16
Ultra high speed complementary MOS device Grant 4,229,756 - Sato , et al. October 21, 1	1980-10-21
Narrow channel MOS devices and method of manufacturing Grant 4,217,599 - Sato , et al. August 12, 1	1980-08-12
Memory Circuit Using Variable Threshold Level Field-effect Device Grant 3,875,567 - Yamazaki , et al. April 1, 1	1975-04-01

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