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name:-0.0016999244689941
name:-0.013416051864624
name:-0.00074005126953125
Yamaguchi, Shinichiro Patent Filings

Yamaguchi, Shinichiro

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yamaguchi, Shinichiro.The latest application filed is for "multiplexed computer system".

Company Profile
0.10.1
  • Yamaguchi, Shinichiro - Mito-shi JP
  • Yamaguchi; Shinichiro - Mito JP
  • Yamaguchi; Shinichiro - Hitachi JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Multiplexed computer system
App 20010032301 - Morita, Yuuichiro ;   et al.
2001-10-18
Fault-tolerant computer system
Grant 6,032,265 - Oguro , et al. February 29, 2
2000-02-29
Multiplexed computer system with the capability to copy data from one processor memory to another
Grant 6,003,116 - Morita , et al. December 14, 1
1999-12-14
Uninterruptible clock supply apparatus for fault tolerant computer system
Grant 5,852,728 - Matsuda , et al. December 22, 1
1998-12-22
Dual information processing system having a plurality of data transfer channels
Grant 5,841,963 - Nakamikawa , et al. November 24, 1
1998-11-24
Method of and system for verifying operation concurrence in maintenance/replacement of twin CPUs
Grant 5,737,513 - Matsuda , et al. April 7, 1
1998-04-07
System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension
Grant 5,146,569 - Yamaguchi , et al. September 8, 1
1992-09-08
Suspended instruction restart processing system based on a checkpoint microprogram address
Grant 5,003,458 - Yamaguchi , et al. March 26, 1
1991-03-26
Method for restarting execution interrupted due to page fault in a data processing system
Grant 4,841,439 - Nishikawa , et al. June 20, 1
1989-06-20
Apparatus for performing floating point arithmetic operations and rounding the result thereof
Grant 4,839,846 - Hirose , et al. June 13, 1
1989-06-13
Method and apparatus for controlling interruption in the course of instruction execution in a processor
Grant 4,764,869 - Miyazaki , et al. August 16, 1
1988-08-16

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