| Patent | Date |
|---|
Semiconductor device
Grant 9,503,018 - Tsutsumi , et al. November 22, 2 | 2016-11-22 |
Semiconductor Device
App 20160142011 - TSUTSUMI; Toshiaki ; et al. | 2016-05-19 |
Semiconductor device
Grant 9,252,793 - Tsutsumi , et al. February 2, 2 | 2016-02-02 |
Semiconductor Device
App 20130314165 - Tsutsumi; Toshiaki ; et al. | 2013-11-28 |
Semiconductor Device
App 20120075029 - SEKINE; Yasushi ; et al. | 2012-03-29 |
Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system
Grant RE39,579 - Hatakenaka , et al. April 17, 2 | 2007-04-17 |
Dynamic associative memory device
Grant 6,859,377 - Yamagata February 22, 2 | 2005-02-22 |
Data bus
Grant 6,844,754 - Yamagata January 18, 2 | 2005-01-18 |
Dynamic associative memory device
App 20040136216 - Yamagata, Tadato | 2004-07-15 |
Data bus
App 20030234664 - Yamagata, Tadato | 2003-12-25 |
Semiconductor memory module and register buffer device for use in the same
Grant 6,650,588 - Yamagata November 18, 2 | 2003-11-18 |
Semiconductor integrated circuit device having hierarchical power source arrangement
Grant 6,643,208 - Yamagata , et al. November 4, 2 | 2003-11-04 |
Semiconductor integrated circuit device having hierarchical power source arrangement
App 20030189869 - Yamagata, Tadato ; et al. | 2003-10-09 |
Semiconductor memory module and register buffer device for use in the same
App 20030026155 - Yamagata, Tadato | 2003-02-06 |
Memory module
Grant 6,515,922 - Yamagata February 4, 2 | 2003-02-04 |
Semiconductor integrated circuit device having hierarchical power source arrangement
App 20020057618 - Yamagata, Tadato ; et al. | 2002-05-16 |
Multi-bank semiconductor memory device suitable for integration with logic
Grant 6,310,815 - Yamagata , et al. October 30, 2 | 2001-10-30 |
Semiconductor integrated circuit device having hierarchical power source arrangement
App 20010019502 - Yamagata, Tadato ; et al. | 2001-09-06 |
Semiconductor integrated circuit device having hierarchical power source arrangement
Grant 6,246,625 - Yamagata , et al. June 12, 2 | 2001-06-12 |
Semiconductor integrated circuit device with large internal bus width, including memory and logic circuit
Grant 6,163,493 - Yamagata , et al. December 19, 2 | 2000-12-19 |
Semiconductor integrated circuit device having hierarchical power source arrangement
Grant 5,959,927 - Yamagata , et al. September 28, 1 | 1999-09-28 |
Semiconductor memory device capable of block writing in large bus width
Grant 5,930,194 - Yamagata , et al. July 27, 1 | 1999-07-27 |
Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core
Grant 5,910,181 - Hatakenaka , et al. June 8, 1 | 1999-06-08 |
Semiconductor memory device realizing high speed access and low power consumption with redundant circuit
Grant 5,798,974 - Yamagata August 25, 1 | 1998-08-25 |
Semiconductor integrated circuit device having hierarchical power source arrangement
Grant 5,726,946 - Yamagata , et al. March 10, 1 | 1998-03-10 |
Fast memory device allowing suppression of peak value of operational current
Grant 5,726,943 - Yamagata , et al. March 10, 1 | 1998-03-10 |
Static type semiconductor device operable at a low voltage with small power consumption
Grant 5,677,889 - Haraguchi , et al. October 14, 1 | 1997-10-14 |
Boosting circuit improved to operate in a wider range of power supply voltage, and a semiconductor memory and a semiconductor integrated circuit device using the same
Grant 5,404,329 - Yamagata , et al. April 4, 1 | 1995-04-04 |
Content addressable memory device and a method of disabling a coincidence word thereof
Grant 5,388,066 - Hamamoto , et al. February 7, 1 | 1995-02-07 |
Dynamic type semiconductor memory device having reduced peak current during refresh mode and method of operating the same
Grant 5,367,493 - Yamagata November 22, 1 | 1994-11-22 |
Dynamic content addressable memory device and a method of operating thereof
Grant 5,319,589 - Yamagata , et al. June 7, 1 | 1994-06-07 |
Input circuit of a semiconductor device
Grant 5,208,474 - Yamagata , et al. May 4, 1 | 1993-05-04 |
Semiconductor integrated circuit device having improved stacked capacitor and manufacturing method therefor
Grant 5,146,300 - Hamamoto , et al. September 8, 1 | 1992-09-08 |
Content addressable semiconductor memory device and operating method therefor
Grant 5,126,968 - Hamamoto , et al. June 30, 1 | 1992-06-30 |
Semiconductor memory device with logic level responsive testing circuit and method therefor
Grant 5,016,220 - Yamagata May 14, 1 | 1991-05-14 |
Electric fuse for a redundancy circuit
Grant 4,984,054 - Yamada , et al. January 8, 1 | 1991-01-08 |
Semiconductor device for multiple packaging configurations
Grant 4,974,053 - Kinoshita , et al. November 27, 1 | 1990-11-27 |
Dynamic random access memory device with internal refresh
Grant 4,870,620 - Yamagata , et al. September 26, 1 | 1989-09-26 |
CMOS reference voltage generator employing separate reference circuits for each output transistor
Grant 4,788,455 - Mori , et al. November 29, 1 | 1988-11-29 |
CMOS dynamic random access memory
Grant 4,780,850 - Miyamoto , et al. October 25, 1 | 1988-10-25 |
Semiconductor memory
Grant 4,734,889 - Mashiko , et al. March 29, 1 | 1988-03-29 |
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