| Patent | Date |
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Pen Nib
App 20160246391 - Yamada; Michihiro ; et al. | 2016-08-25 |
Semiconductor memory device and method of data transfer therefor
Grant 5,481,496 - Kobayashi , et al. January 2, 1 | 1996-01-02 |
Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit
Grant 5,323,348 - Mori , et al. June 21, 1 | 1994-06-21 |
Semiconductor memory device and method of testing the same
Grant 5,305,261 - Furutani , et al. April 19, 1 | 1994-04-19 |
Input circuit of a semiconductor device
Grant 5,208,474 - Yamagata , et al. May 4, 1 | 1993-05-04 |
Method of fibricating a semiconductor device having a trench
Grant 5,112,771 - Ishii , et al. May 12, 1 | 1992-05-12 |
Delay circuit employing different threshold FET's
Grant 5,063,313 - Kikuda , et al. November 5, 1 | 1991-11-05 |
Dynamic random access memory with FET equalization of bit lines
Grant 5,053,997 - Miyamato , et al. October 1, 1 | 1991-10-01 |
Electric fuse for a redundancy circuit
Grant 4,984,054 - Yamada , et al. January 8, 1 | 1991-01-08 |
Arbiter circuit for processing concurrent requests for access to shared resources
Grant 4,962,379 - Yasuda , et al. October 9, 1 | 1990-10-09 |
Method of and apparatus for reducing current of semiconductor memory device
Grant 4,933,902 - Yamada , et al. June 12, 1 | 1990-06-12 |
MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform
Grant 4,931,668 - Kikuda , et al. June 5, 1 | 1990-06-05 |
Delay circuit
Grant 4,914,326 - Kikuda , et al. April 3, 1 | 1990-04-03 |
Dynamic random access memory device with internal refresh
Grant 4,870,620 - Yamagata , et al. September 26, 1 | 1989-09-26 |
Wafer scale integration semiconductor device having improved chip power-supply connection arrangement
Grant 4,855,613 - Yamada , et al. August 8, 1 | 1989-08-08 |
Semiconductor memory having divided bit lines and individual sense amplifiers
Grant 4,803,663 - Miyamoto , et al. February 7, 1 | 1989-02-07 |
Semiconductor memory device with bit line sense amplifiers
Grant 4,792,927 - Miyamoto , et al. December 20, 1 | 1988-12-20 |
CMOS reference voltage generator employing separate reference circuits for each output transistor
Grant 4,788,455 - Mori , et al. November 29, 1 | 1988-11-29 |
CMOS dynamic random access memory
Grant 4,780,850 - Miyamoto , et al. October 25, 1 | 1988-10-25 |
Dynamic ram having folded bit line structure
Grant 4,739,500 - Miyamoto , et al. April 19, 1 | 1988-04-19 |
CMOS decoder circuit resistant to latch-up
Grant 4,724,341 - Yamada , et al. February 9, 1 | 1988-02-09 |
Semiconductor memory device
Grant 4,689,770 - Miyamoto , et al. August 25, 1 | 1987-08-25 |
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