Yagishita; Yoshimasa

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yagishita; Yoshimasa.The latest application filed is for "semiconductor memory test method and semiconductor memory".

Company Profile

0.12.14

Yagishita; Yoshimasa - Hino JP
Yagishita; Yoshimasa - Yokohama JP
Yagishita; Yoshimasa - Kawasaki JP
Yagishita; Yoshimasa - Kawasaki-shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor memory test method and semiconductor memory Grant 9,269,456 - Mori , et al. February 23, 2	2016-02-23
Semiconductor Memory Test Method And Semiconductor Memory App 20130170308 - MORI; Kaoru ; et al.	2013-07-04
Semiconductor memory, system, operating method of semiconductor memory, and manufacturing method of semiconductor memory Grant 8,050,121 - Yagishita November 1, 2	2011-11-01
Semiconductor Memory, System, Operating Method Of Semiconductor Memory, And Manufacturing Method Of Semiconductor Memory App 20100322024 - YAGISHITA; Yoshimasa	2010-12-23
Semiconductor memory device Grant 6,999,358 - Yagishita , et al. February 14, 2	2006-02-14
Semiconductor memory having dummy regions in memory cell array Grant 6,987,698 - Bando , et al. January 17, 2	2006-01-17
Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit Grant 6,876,225 - Yagishita , et al. April 5, 2	2005-04-05
Semiconductor memory Grant 6,754,126 - Yamaguchi , et al. June 22, 2	2004-06-22
Semiconductor memory Grant 6,728,157 - Yagishita , et al. April 27, 2	2004-04-27
Semiconductor memory device App 20040062114 - Yagishita, Yoshimasa ; et al.	2004-04-01
Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit Grant 6,696,859 - Yagishita , et al. February 24, 2	2004-02-24
Semiconductor memory App 20040004883 - Yagishita, Yoshimasa ; et al.	2004-01-08
Semiconductor memory device Grant 6,654,298 - Yagishita , et al. November 25, 2	2003-11-25
Method for operating a semiconductor memory device having a plurality of operating modes for controlling an internal circuit Grant 6,629,224 - Suzuki , et al. September 30, 2	2003-09-30
Input signal receiving circuit for semiconductor integrated circuit Grant 6,532,179 - Yagishita March 11, 2	2003-03-11
Semiconductor memory App 20030026161 - Yamaguchi, Shusaku ; et al.	2003-02-06
Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit App 20020175708 - Yagishita, Yoshimasa ; et al.	2002-11-28
Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit App 20020158667 - Yagishita, Yoshimasa ; et al.	2002-10-31
Semiconductor integrated circuit App 20020145935 - Yagishita, Yoshimasa	2002-10-10
Semiconductor memory device App 20020141270 - Yagishita, Yoshimasa ; et al.	2002-10-03
Semiconductor memory device App 20020141262 - Yagishita, Yoshimasa ; et al.	2002-10-03
Input/output interfacing circuit, input/output interface, and semiconductor device having input/output interfacing circuit App 20020053926 - Yagishita, Yoshimasa ; et al.	2002-05-09
Semiconductor integrated circuit App 20010026479 - Yagishita, Yoshimasa	2001-10-04
Semiconductor integrated circuit App 20010008280 - Yagishita, Yoshimasa	2001-07-19
Semiconductor integrated circuit App 20010007776 - Yagishita, Yoshimasa	2001-07-12
Memory device Grant 6,104,659 - Yagishita , et al. August 15, 2	2000-08-15

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.