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Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices Grant 8,598,005 - Chan , et al. December 3, 2 | 2013-12-03 |
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Oro And Orpro With Bit Line Trench To Suppress Transport Program Disturb App 20110278660 - Cheng; Ning ;   et al. | 2011-11-17 |
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Si Trench Between Bitline Hdp For Bvdss Improvement App 20090152669 - Xue; Lei ;   et al. | 2009-06-18 |
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Memory Cell System With Charge Trap App 20080083946 - Fang; Shenqing ;   et al. | 2008-04-10 |
Flash memory cell structure for increased program speed and erase speed App 20080079061 - Ding; Meng ;   et al. | 2008-04-03 |
Memory Cell System With Multiple Nitride Layers App 20080023750 - Xue; Lei ;   et al. | 2008-01-31 |
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Memory Cell System Using Silicon-rich Nitride App 20070215932 - Ding; Meng ;   et al. | 2007-09-20 |
Memory device with barrier layer Grant 7,053,445 - Suh , et al. May 30, 2 | 2006-05-30 |