loadpatents
name:-0.021263122558594
name:-0.019171953201294
name:-0.003939151763916
XIAO; Changyong Patent Filings

XIAO; Changyong

Patent Applications and Registrations

Patent applications and USPTO patent grants for XIAO; Changyong.The latest application filed is for "method for forming semiconductor structure".

Company Profile
3.18.19
  • XIAO; Changyong - Shanghai CN
  • Xiao; Changyong - Leuven BE
  • Xiao; Changyong - Mechanicville NY
  • Xiao; Changyong - Mechanicsville NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method For Forming Semiconductor Structure
App 20220130679 - WANG; Hua ;   et al.
2022-04-28
Method For Processing A Finfet Device
App 20210305412 - Chan; Boon Teik ;   et al.
2021-09-30
Semiconductor devices and fabrication methods thereof
Grant 10,847,425 - Lu , et al. November 24, 2
2020-11-24
Semiconductor Devices And Fabrication Methods Thereof
App 20200020590 - LU; Yi ;   et al.
2020-01-16
FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same
Grant 10,032,910 - Wu , et al. July 24, 2
2018-07-24
Gate Structures With Low Resistance
App 20180158821 - XIAO; Changyong ;   et al.
2018-06-07
Non-planar semiconductor device with multiple-head epitaxial structure on fin
Grant 9,793,358 - Wu , et al. October 17, 2
2017-10-17
Mixed N/P-type fin semiconductor structure with epitaxial materials having increased surface area through multiple epitaxial heads
Grant 9,508,794 - Wu , et al. November 29, 2
2016-11-29
Finfet Devices Having Asymmetrical Epitaxially-grown Source And Drain Regions And Methods Of Forming The Same
App 20160315172 - Wu; Xusheng ;   et al.
2016-10-27
Different Height Of Fins In Semiconductor Structure
App 20160315084 - WU; Xusheng ;   et al.
2016-10-27
Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device
Grant 9,419,015 - Wu , et al. August 16, 2
2016-08-16
Shallow trench isolation integration methods and devices formed thereby
Grant 9,385,192 - Shen , et al. July 5, 2
2016-07-05
Threshold voltage control for mixed-type non-planar semiconductor devices
Grant 9,362,284 - Togo , et al. June 7, 2
2016-06-07
Increased Surface Area Of Epitaxial Structures In A Mixed N/p Type Fin Semiconductor Structure With Multiple Epitaxial Heads
App 20160155799 - WU; Xusheng ;   et al.
2016-06-02
Method Of Improved Ca/cb Contact And Device Thereof
App 20160126336 - WU; Xusheng ;   et al.
2016-05-05
T-shaped contacts for semiconductor device
Grant 9,299,608 - Wu , et al. March 29, 2
2016-03-29
Method for increasing a surface area of epitaxial structures in a mixed N/P type fin semiconductor structure by forming multiple epitaxial heads
Grant 9,275,906 - Wu , et al. March 1, 2
2016-03-01
Product Comprised Of Finfet Devices With Single Diffusion Break Isolation Structures
App 20160049468 - Wu; Xusheng ;   et al.
2016-02-18
Threshold Voltage Control For Mixed-type Non-planar Semiconductor Devices
App 20160049400 - TOGO; Mitsuhiro ;   et al.
2016-02-18
Product comprised of FinFET devices with single diffusion break isolation structures
Grant 9,263,516 - Wu , et al. February 16, 2
2016-02-16
Threshold Voltage Control For Mixed-type Non-planar Semiconductor Devices
App 20150380409 - TOGO; Mitsuhiro ;   et al.
2015-12-31
Threshold voltage control for mixed-type non-planar semiconductor devices
Grant 9,209,186 - Togo , et al. December 8, 2
2015-12-08
T-shaped Contacts For Semiconductor Device
App 20150332963 - WU; Xusheng ;   et al.
2015-11-19
Shallow Trench Isolation Integration Methods And Devices Formed Thereby
App 20150333121 - Shen; Hongliang ;   et al.
2015-11-19
Multiple Epitaxial Head Raised Semiconductor Structure And Method Of Making Same
App 20150318351 - WU; Xusheng ;   et al.
2015-11-05
Mixed N/p Type Non-planar Semiconductor Structure With Multiple Epitaxial Heads And Method Of Making Same
App 20150318217 - WU; Xusheng ;   et al.
2015-11-05
Replacement Low-k Spacer
App 20150311083 - XIAO; Changyong ;   et al.
2015-10-29
Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product
Grant 9,171,752 - Wu , et al. October 27, 2
2015-10-27
Replacement low-K spacer
Grant 9,159,567 - Xiao , et al. October 13, 2
2015-10-13
Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
Grant 9,123,783 - Wang , et al. September 1, 2
2015-09-01
T-shaped single diffusion barrier with single mask approach process flow
Grant 9,123,773 - Shen , et al. September 1, 2
2015-09-01
Shallow trench isolation integration methods and devices formed thereby
Grant 9,123,771 - Shen , et al. September 1, 2
2015-09-01
Methods for forming FinFETs with reduced series resistance
Grant 9,087,720 - Wu , et al. July 21, 2
2015-07-21
Contact Liner And Methods Of Fabrication Thereof
App 20140327139 - YU; Jialin ;   et al.
2014-11-06
Shallow Trench Isolation Integration Methods And Devices Formed Thereby
App 20140227858 - Shen; Hongliang ;   et al.
2014-08-14
Integrated Circuits And Methods Of Forming Integrated Circuits With Interlayer Dielectric Protection
App 20140131881 - Wang; Xin ;   et al.
2014-05-15
Fin removal method
Grant 8,617,996 - Chi , et al. December 31, 2
2013-12-31

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed