Xcelsis Corporation
Patent Applications and Registrations
Patent applications and USPTO patent grants for Xcelsis Corporation.The latest application filed is for "direct-bonded native interconnects and active base die".
Company Profile
88.80.72
- Xcelsis Corporation - San Jose CA
Patent Activity
| Patent | Date |
|---|---|
| 3D NAND--high aspect ratio strings and channels Grant 11,404,439 - Katkar , et al. August 2, 2 | 2022-08-02 |
| Direct-Bonded Native Interconnects And Active Base Die App 20220238339 - DeLaCruz; Javier A. ; et al. | 2022-07-28 |
| Systems and methods for releveled bump planes for chiplets Grant 11,348,898 - Delacruz , et al. May 31, 2 | 2022-05-31 |
| Three Dimensional Circuit Implementing Machine Trained Network App 20220108161 - Teig; Steven L. ; et al. | 2022-04-07 |
| Direct-bonded native interconnects and active base die Grant 11,289,333 - Delacruz , et al. March 29, 2 | 2022-03-29 |
| 3d Processor App 20220068890 - Teig; Steven L. ; et al. | 2022-03-03 |
| Configurable smart object system with clip-based connectors Grant 11,239,587 - Haba , et al. February 1, 2 | 2022-02-01 |
| Back Biasing of FD-SOI Circuit Block App 20220020741 - Delacruz; Javier A. ; et al. | 2022-01-20 |
| Three dimensional circuit implementing machine trained network Grant 11,176,450 - Teig , et al. November 16, 2 | 2021-11-16 |
| Systems and methods for inter-die block level design Grant 11,157,670 - Delacruz , et al. October 26, 2 | 2021-10-26 |
| 3D processor having stacked integrated circuit die Grant 11,152,336 - Teig , et al. October 19, 2 | 2021-10-19 |
| Abstracted NAND logic in stacks Grant 11,139,283 - Delacruz , et al. October 5, 2 | 2021-10-05 |
| Back biasing of FD-SOI circuit blocks Grant 11,127,738 - Delacruz , et al. September 21, 2 | 2021-09-21 |
| Systems and Methods for Releveled Bump Planes for Chiplets App 20210249383 - Delacruz; Javier A. ; et al. | 2021-08-12 |
| Transistor Level Interconnection Methodologies Utilizing 3D Interconnects App 20210217858 - Delacruz; Javier A. ; et al. | 2021-07-15 |
| Stacked Ic Structure With Orthogonal Interconnect Layers App 20210202387 - Mohammed; Ilyas ; et al. | 2021-07-01 |
| 3d Chip Sharing Data Bus App 20210202445 - DeLaCruz; Javier A. ; et al. | 2021-07-01 |
| Systems and Methods for Releveled Bump Planes for Chiplets App 20210175206 - Delacruz; Javier A. ; et al. | 2021-06-10 |
| Hard IP Blocks With Physically Bidirectional Passageways App 20210166995 - Delacruz; Javier A. | 2021-06-03 |
| Transistor level interconnection methodologies utilizing 3D interconnects Grant 10,991,804 - Delacruz , et al. April 27, 2 | 2021-04-27 |
| 3D chip sharing power interconnect layer Grant 10,978,348 - DeLaCruz , et al. April 13, 2 | 2021-04-13 |
| 3d Chip With Shared Clock Distribution Network App 20210104436 - DeLaCruz; Javier ; et al. | 2021-04-08 |
| Time borrowing between layers of a three dimensional chip stack Grant 10,970,627 - Teig , et al. April 6, 2 | 2021-04-06 |
| Stacked IC structure with system level wiring on multiple sides of the IC die Grant 10,950,547 - Mohammed , et al. March 16, 2 | 2021-03-16 |
| 3d Nand - High Aspect Ratio Strings And Channels App 20210074723 - Katkar; Rajesh ; et al. | 2021-03-11 |
| Hard IP blocks with physically bidirectional passageways Grant 10,923,413 - Delacruz February 16, 2 | 2021-02-16 |
| Systems and methods for releveled bump planes for chiplets Grant 10,910,344 - Delacruz , et al. February 2, 2 | 2021-02-02 |
| Face-to-face mounted IC dies with orthogonal top interconnect layers Grant 10,892,252 - Nequist , et al. January 12, 2 | 2021-01-12 |
| 3D chip with shared clock distribution network Grant 10,886,177 - DeLaCruz , et al. January 5, 2 | 2021-01-05 |
| Device Disaggregation For Improved Performance App 20200403006 - Delacruz; Javier A. ; et al. | 2020-12-24 |
| Head mounted viewer for AR and VR scenes Grant 10,852,545 - Mohammed , et al. December 1, 2 | 2020-12-01 |
| Systems And Methods For Inter-die Block Level Design App 20200356714 - DELACRUZ; Javier A. ; et al. | 2020-11-12 |
| Direct-Bonded Native Interconnects And Active Base Die App 20200357641 - Delacruz; Javier A. ; et al. | 2020-11-12 |
| Direct-bonded native interconnects and active base die Grant 10,832,912 - Delacruz , et al. November 10, 2 | 2020-11-10 |
| 3D NAND--high aspect ratio strings and channels Grant 10,784,282 - Katkar , et al. Sept | 2020-09-22 |
| Time Borrowing Between Layers Of A Three Dimensional Chip Stack App 20200293872 - Teig; Steven L. ; et al. | 2020-09-17 |
| 3D Chip with Shared Clock Distribution Network App 20200294858 - DeLaCruz; Javier ; et al. | 2020-09-17 |
| Self repairing neural network Grant 10,762,420 - Teig , et al. Sep | 2020-09-01 |
| Stacked IC Structure with System Level Wiring on Multiple Sides of the IC Die App 20200273798 - Mohammed; Ilyas ; et al. | 2020-08-27 |
| Configurable smart object system with magnetic contacts and magnetic assembly Grant 10,734,759 - Haba , et al. | 2020-08-04 |
| Three dimensional chip structure implementing machine trained network Grant 10,719,762 - Teig , et al. | 2020-07-21 |
| 3d Processor App 20200227389 - Teig; Steven L. ; et al. | 2020-07-16 |
| 3D Chip Sharing Power Interconnect Layer App 20200219771 - DeLaCruz; Javier ; et al. | 2020-07-09 |
| Device disaggregation for improved performance Grant 10,700,094 - Delacruz , et al. | 2020-06-30 |
| 3d Nand - High Aspect Ratio Strings And Channels App 20200203368 - Katkar; Rajesh ; et al. | 2020-06-25 |
| Abstracted NAND Logic In Stacks App 20200203330 - Delacruz; Javier A. ; et al. | 2020-06-25 |
| Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers App 20200203318 - Nequist; Eric M. ; et al. | 2020-06-25 |
| Stacked Architecture For Three-dimensional Nand App 20200203316 - Morein; Stephen ; et al. | 2020-06-25 |
| Direct-bonded Native Interconnects And Active Base Die App 20200194262 - DELACRUZ; Javier A. ; et al. | 2020-06-18 |
| Self healing compute array Grant 10,684,929 - Delacruz , et al. | 2020-06-16 |
| 3D chip sharing power circuit Grant 10,672,663 - DeLaCruz , et al. | 2020-06-02 |
| 3D compute circuit with high density Z-axis interconnects Grant 10,672,744 - Teig , et al. | 2020-06-02 |
| 3D Compute circuit with high density z-axis interconnects Grant 10,672,743 - Teig , et al. | 2020-06-02 |
| 3D processor Grant 10,672,745 - Teig , et al. | 2020-06-02 |
| Systems and methods for inter-die block level design Grant 10,664,564 - Delacruz , et al. | 2020-05-26 |
| Time borrowing between layers of a three dimensional chip stack Grant 10,607,136 - Teig , et al. | 2020-03-31 |
| 3D chip sharing data bus circuit Grant 10,600,780 - DeLaCruz , et al. | 2020-03-24 |
| 3D chip sharing data bus Grant 10,600,735 - DeLaCruz , et al. | 2020-03-24 |
| 3D chip sharing power interconnect layer Grant 10,600,691 - DeLaCruz , et al. | 2020-03-24 |
| 3D chip with shielded clock lines Grant 10,593,667 - DeLaCruz , et al. | 2020-03-17 |
| Head Mounted Viewer For Ar And Vr Scenes App 20200081250 - MOHAMMED; Ilyas ; et al. | 2020-03-12 |
| Stacked Optical Waveguides App 20200081251 - MOHAMMED; Ilyas ; et al. | 2020-03-12 |
| 3D chip sharing clock interconnect layer Grant 10,586,786 - DeLaCruz , et al. | 2020-03-10 |
| Integrated Voltage Regulator And Passive Components App 20200075553 - DELACRUZ; Javier A. ; et al. | 2020-03-05 |
| Stacked IC structure with system level wiring on multiple sides of the IC die Grant 10,580,735 - Mohammed , et al. | 2020-03-03 |
| Face-to-face mounted IC dies with orthogonal top interconnect layers Grant 10,580,757 - Nequist , et al. | 2020-03-03 |
| Device Disaggregation For Improved Performance App 20200051999 - Delacruz; Javier A. ; et al. | 2020-02-13 |
| Direct-bonded native interconnects and active base die Grant 10,522,352 - Delacruz , et al. Dec | 2019-12-31 |
| Systems and methods for inter-die block level design App 20190392104 - DELACRUZ; Javier A ; et al. | 2019-12-26 |
| Systems and methods for releveled bump planes for chiplets App 20190393190 - DELACRUZ; Javier A. ; et al. | 2019-12-26 |
| Eliminating defects in stacks App 20190393204 - DELACRUZ; Javier A. ; et al. | 2019-12-26 |
| Hard IP Blocks WIth Physically Bidirectional Passageways App 20190371708 - Delacruz; Javier A. | 2019-12-05 |
| Transistor Level Interconnection Methodologies Utilizing 3d Interconnects App 20190305093 - Delacruz; Javier A. ; et al. | 2019-10-03 |
| Configurable Smart Object System With Grid Or Frame-based Connectors App 20190280421 - HABA; Belgacem ; et al. | 2019-09-12 |
| Configurable Smart Object System With Clip-based Connectors App 20190280408 - HABA; Belgacem ; et al. | 2019-09-12 |
| Configurable Smart Object System With Magnetic Contacts And Magnetic Assembly App 20190280428 - HABA; Belgacem ; et al. | 2019-09-12 |
| Back biasing of FD-SOI circuit blocks App 20190252375 - DELACRUZ; Javier A. ; et al. | 2019-08-15 |
| Wafer testing without direct probing Grant 10,295,588 - Delacruz , et al. | 2019-05-21 |
| 3D Compute Circuit with High Density Z-Axis Interconnects App 20190123023 - Teig; Steven L. ; et al. | 2019-04-25 |
| 3D Compute Circuit with High Density Z-Axis Interconnects App 20190123022 - Teig; Steven L. ; et al. | 2019-04-25 |
| 3D Processor App 20190123024 - Teig; Steven L. ; et al. | 2019-04-25 |
| Configurable Smart Object System With Standard Connectors For Adding Artificial Intelligence To Appliances, Vehicles, And Devices App 20190097362 - HABA; Belgacem ; et al. | 2019-03-28 |
| Time Borrowing Between Layers Of A Three Dimensional Chip Stack App 20190042912 - Teig; Steven L. ; et al. | 2019-02-07 |
| Self Repairing Neural Network App 20190042377 - Teig; Steven L. ; et al. | 2019-02-07 |
| Three Dimensional Chip Structure Implementing Machine Trained Network App 20190043832 - Teig; Steven L. ; et al. | 2019-02-07 |
| Three Dimensional Circuit Implementing Machine Trained Network App 20190042929 - Teig; Steven L. ; et al. | 2019-02-07 |
| Configurable Smart Object System With Methods Of Making Modules And Contactors App 20190029132 - HABA; Belgacem ; et al. | 2019-01-24 |
| 3D Chip Sharing Clock Interconnect Layer App 20180350775 - DeLaCruz; Javier ; et al. | 2018-12-06 |
| 3D Chip Sharing Power Interconnect Layer App 20180330992 - DeLaCruz; Javier ; et al. | 2018-11-15 |
| 3D Chip with Shielded Clock Lines App 20180331095 - DeLaCruz; Javier ; et al. | 2018-11-15 |
| 3D Chip Sharing Power Circuit App 20180330993 - DeLaCruz; Javier ; et al. | 2018-11-15 |
| 3D Chip Sharing Data Bus Circuit App 20180331094 - DeLaCruz; Javier ; et al. | 2018-11-15 |
| 3D Chip Sharing Data Bus App 20180331038 - DeLaCruz; Javier ; et al. | 2018-11-15 |
| Stacked IC Structure with System Level Wiring on Multiple Sides of the IC Die App 20180331037 - Mohammed; Ilyas ; et al. | 2018-11-15 |
| Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers App 20180331072 - Nequist; Eric M. ; et al. | 2018-11-15 |
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