loadpatents
name:-0.011752128601074
name:-0.010753870010376
name:-0.0044958591461182
Wu; Ze-Ming Patent Filings

Wu; Ze-Ming

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; Ze-Ming.The latest application filed is for "method of manufacturing semiconductor device and system for same".

Company Profile
2.11.12
  • Wu; Ze-Ming - Hsinchu TW
  • Wu; Ze-Ming - Tainan TW
  • Wu; Ze-Ming - Tainan City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuit layout generation method and system
Grant 11,392,749 - Su , et al. July 19, 2
2022-07-19
Method Of Manufacturing Semiconductor Device And System For Same
App 20220012401 - SU; Ke-Ying ;   et al.
2022-01-13
Integrated Circuit Layout Generation Method And System
App 20210073454 - SU; Ke-Ying ;   et al.
2021-03-11
Integrated circuit modeling methods and systems
Grant 10,846,456 - Su , et al. November 24, 2
2020-11-24
Integrated Circuit Modeling Methods And Systems
App 20190340328 - SU; Ke-Ying ;   et al.
2019-11-07
System and method for creating hybrid resistance and capacitance (RC) netlist using three-dimensional RC extraction and 2.5 dimensional RC extraction
Grant 9,582,630 - Wu , et al. February 28, 2
2017-02-28
Cell Based Hybrid Rc Extraction
App 20160063165 - Wu; Ze-Ming ;   et al.
2016-03-03
Semiconductor device design method, system and computer-readable medium
Grant 8,904,337 - Yang , et al. December 2, 2
2014-12-02
Tool and method for modeling interposer RC couplings
Grant 8,856,710 - Yeh , et al. October 7, 2
2014-10-07
Parasitic Capacitance Extraction for FinFETs
App 20140258962 - Ho; Chia-Ming ;   et al.
2014-09-11
Parasitic capacitance extraction for FinFETs
Grant 8,826,213 - Ho , et al. September 2, 2
2014-09-02
Semiconductor Device Design Method, System And Computer-readable Medium
App 20140189635 - YANG; Ching-Shun ;   et al.
2014-07-03
Semiconductor device design method, system and computer-readable medium
Grant 8,707,245 - Yang , et al. April 22, 2
2014-04-22
Rc Extraction Methodology For Floating Silicon Substrate With Tsv
App 20140082578 - Wu; Ze-Ming ;   et al.
2014-03-20
RC extraction methodology for floating silicon substrate with TSV
Grant 8,607,179 - Wu , et al. December 10, 2
2013-12-10
Semiconductor Device Design Method, System And Computer-readable Medium
App 20130227501 - YANG; Ching-Shun ;   et al.
2013-08-29
RC Extraction Methodology for Floating Silicon Substrate with TSV
App 20130139121 - Wu; Ze-Ming ;   et al.
2013-05-30
Tool And Method For Modeling Interposer Rc Couplings
App 20130007692 - Yeh; Chao-Yang ;   et al.
2013-01-03

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