Wu; Yung-Hsu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; Yung-Hsu.The latest application filed is for "integrated circuit interconnect structures with air gaps".

Company Profile

15.45.46

Wu; Yung-Hsu - Taipei TW
Wu; Yung-Hsu - Taipei City TW
Wu; Yung-Hsu - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-metal fill with self-aligned patterning and dielectric with voids Grant 11,422,475 - Yang , et al. August 23, 2	2022-08-23
Method for forming semiconductor device with self-aligned conductive features Grant 11,404,367 - Yang , et al. August 2, 2	2022-08-02
Method of fabricating semiconductor device with reduced trench distortions Grant 11,387,113 - Yen , et al. July 12, 2	2022-07-12
Integrated Circuit Interconnect Structures with Air Gaps App 20220157720 - Yang; Tai-I ; et al.	2022-05-19
Integrated circuit interconnect structures with air gaps Grant 11,244,898 - Yang , et al. February 8, 2	2022-02-08
Using A Self-Assembly Layer To Facilitate Selective Formation of An Etching Stop Layer App 20210351034 - Lee; Shao-Kuan ; et al.	2021-11-11
Using a self-assembly layer to facilitate selective formation of an etching stop layer Grant 11,069,526 - Lee , et al. July 20, 2	2021-07-20
Semiconductor device having voids and method of forming same Grant 11,011,421 - Wu , et al. May 18, 2	2021-05-18
Method and Apparatus for Forming Self-Aligned Via with Selectively Deposited Etching Stop Layer App 20210098362 - Wu; Yung-Hsu ; et al.	2021-04-01
Barrier-Less Structures App 20210057273 - Chen; Hsin-Ping ; et al.	2021-02-25
Method Of Fabricating Semiconductor Device With Reduced Trench Distortions App 20210057231 - Yen; Yung-Sung ; et al.	2021-02-25
Spacer-damage-free etching Grant 10,916,443 - Huang , et al. February 9, 2	2021-02-09
Semiconductor Device Having Voids and Method of Forming Same App 20200411375 - Wu; Yung-Hsu ; et al.	2020-12-31
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Grant 10,867,913 - Wu , et al. December 15, 2	2020-12-15
Method For Forming Semiconductor Device With Self-aligned Conductive Features App 20200343180 - YANG; Tai-I ; et al.	2020-10-29
Method of fabricating semiconductor device with reduced trench distortions Grant 10,818,509 - Yen , et al. October 27, 2	2020-10-27
Semiconductor device having voids and method of forming same Grant 10,784,160 - Wu , et al. Sept	2020-09-22
Structure and formation method of semiconductor device with self-aligned conductive features Grant 10,714,421 - Yang , et al.	2020-07-14
Multi-metal Fill With Self-aligned Patterning And Dielectric With Voids App 20200124985 - Yang; Tai-I ; et al.	2020-04-23
Multi-metal fill with self-aligned patterning and dielectric with voids Grant 10,534,273 - Yang , et al. Ja	2020-01-14
Using A Self-assembly Layer To Facilitate Selective Formation Of An Etching Stop Layer App 20200006060 - Lee; Shao-Kuan ; et al.	2020-01-02
Integrated Circuit Interconnect Structures with Air Gaps App 20200006228 - Yang; Tai-I ; et al.	2020-01-02
Spacer-damage-free Etching App 20190252204 - Huang; Tsung-Min ; et al.	2019-08-15
Semiconductor Device having Voids and Method of Forming Same App 20190252249 - Wu; Yung-Hsu ; et al.	2019-08-15
Spacer-damage-free etching Grant 10,283,371 - Huang , et al.	2019-05-07
Method of Fabricating Semiconductor Device with Reduced Trench Distortions App 20190122895 - Yen; Yung-Sung ; et al.	2019-04-25
Semiconductor device having voids and method of forming same Grant 10,269,634 - Wu , et al.	2019-04-23
Structure And Formation Method Of Semiconductor Device With Self-aligned Conductive Features App 20190067187 - YANG; Tai-I ; et al.	2019-02-28
Method of double patterning lithography process using plurality of mandrels for integrated circuit applications Grant 10,170,306 - Lee , et al. J	2019-01-01
Method of fabricating semiconductor device with reduced trench distortions Grant 10,163,654 - Yen , et al. Dec	2018-12-25
Method And Apparatus For Forming Self-aligned Via With Selectively Deposited Etching Stop Layer App 20180211911 - Wu; Yung-Hsu ; et al.	2018-07-26
Lithography using high selectivity spacers for pitch reduction Grant 10,014,175 - Chang , et al. July 3, 2	2018-07-03
Multi-metal Fill With Self-aligned Patterning And Dielectric With Voids App 20180164698 - YANG; Tai-I ; et al.	2018-06-14
Method of forming an interconnect structure for a semiconductor device Grant 9,997,404 - Wu , et al. June 12, 2	2018-06-12
Trench formation using horn shaped spacer Grant 9,947,535 - Huang , et al. April 17, 2	2018-04-17
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Grant 9,922,927 - Wu , et al. March 20, 2	2018-03-20
Self-aligned double spacer patterning process Grant 9,911,646 - Tsai , et al. March 6, 2	2018-03-06
Lithography Using High Selectivity Spacers for Pitch Reduction App 20180012761 - Chang; Yu-Sheng ; et al.	2018-01-11
Self-aligned double spacer patterning process Grant 9,831,117 - Wu , et al. November 28, 2	2017-11-28
Lithography using high selectivity spacers for pitch reduction Grant 9,773,676 - Chang , et al. September 26, 2	2017-09-26
Method And Apparatus For Forming Self-aligned Via With Selectively Deposited Etching Stop Layer App 20170256486 - Wu; Yung-Hsu ; et al.	2017-09-07
Metal lines for interconnect structure and method of manufacturing same Grant 9,735,052 - Tsai , et al. August 15, 2	2017-08-15
Method of Double Patterning Lithography Process Using Plurality of Mandrels for Integrated Circuit Applications App 20170221702 - Lee; Chung-Ju ; et al.	2017-08-03
Self-Aligned Double Spacer Patterning Process App 20170200641 - Tsai; Cheng-Hsiung ; et al.	2017-07-13
Spacer-damage-free Etching App 20170186622 - Huang; Tsung-Min ; et al.	2017-06-29
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Grant 9,659,864 - Wu , et al. May 23, 2	2017-05-23
Method And Apparatus For Forming Self-aligned Via With Selectively Deposited Etching Stop Layer App 20170110397 - Wu; Yung-Hsu ; et al.	2017-04-20
Method of double patterning lithography process using plurality of mandrels for integrated circuit applications Grant 9,627,206 - Lee , et al. April 18, 2	2017-04-18
Method for Interconnect Scheme App 20170103915 - Tsai; Cheng-Hsiung ; et al.	2017-04-13
Self-aligned double spacer patterning process Grant 9,607,850 - Tsai , et al. March 28, 2	2017-03-28
Trench Formation using Horn Shaped Spacer App 20170084460 - Huang; Tsung-Min ; et al.	2017-03-23
Spacer-damage-free etching Grant 9,601,346 - Huang , et al. March 21, 2	2017-03-21
Method for interconnect scheme Grant 9,589,890 - Yao , et al. March 7, 2	2017-03-07
Semiconductor arrangement and formation thereof Grant 9,576,896 - Liao , et al. February 21, 2	2017-02-21
Method for Interconnect Scheme App 20170025346 - Yao; Hsin-Chieh ; et al.	2017-01-26
Method Of Forming An Interconnect Structure For A Semiconductor Device App 20160365276 - WU; Yung-Hsu ; et al.	2016-12-15
Method Of Fabricating Semiconductor Device With Reduced Trench Distortions App 20160358788 - Yen; Yung-Sung ; et al.	2016-12-08
Trench formation using horn shaped spacer Grant 9,514,979 - Huang , et al. December 6, 2	2016-12-06
Method of forming trench cut Grant 9,490,136 - Chang , et al. November 8, 2	2016-11-08
Method of forming an interconnect structure for a semiconductor device Grant 9,431,297 - Wu , et al. August 30, 2	2016-08-30
Semiconductor Arrangement And Formation Thereof App 20160240477 - Liao; Yu-Chieh ; et al.	2016-08-18
Method Of Fabricating Semiconductor Device App 20160240430 - Yen; Yung-Sung ; et al.	2016-08-18
Method of fabricating semiconductor device with reduced trench distortions Grant 9,418,868 - Yen , et al. August 16, 2	2016-08-16
Method of fabricating semiconductor device Grant 9,412,649 - Yen , et al. August 9, 2	2016-08-09
Semiconductor arrangement and formation thereof Grant 9,349,690 - Liao , et al. May 24, 2	2016-05-24
System and method for chemical-mechanical planarization of a metal layer Grant 9,330,989 - Wu , et al. May 3, 2	2016-05-03
Method Of Forming An Interconnect Structure For A Semiconductor Device App 20160099174 - Wu; Yung-Hsu ; et al.	2016-04-07
Method of Double Patterning Lithography process Using Plurality of Mandrels for Integrated Circuit Applications App 20160079063 - Lee; Chung-Ju ; et al.	2016-03-17
Lithography Using High Selectivity Spacers for Pitch Reduction App 20160035571 - Chang; Yu-Sheng ; et al.	2016-02-04
Self-Aligned Double Spacer Patterning Process App 20150380300 - Wu; Yung-Hsu ; et al.	2015-12-31
Trench Formation using Horn Shaped Spacer App 20150371897 - Huang; Tsung-Min ; et al.	2015-12-24
Method of double patterning lithography process using plurality of mandrels for integrated circuit applications Grant 9,209,076 - Yao , et al. December 8, 2	2015-12-08
Self-Aligned Double Spacer Patterning Process App 20150340240 - Tsai; Cheng-Hsiung ; et al.	2015-11-26
Spacer-damage-free Etching App 20150318172 - Huang; Tsung-Min ; et al.	2015-11-05
Lithography using high selectivity spacers for pitch reduction Grant 9,177,797 - Chang , et al. November 3, 2	2015-11-03
Semiconductor Arrangement And Formation Thereof App 20150262937 - Liao; Yu-Chieh ; et al.	2015-09-17
Trench formation using horn shaped spacer Grant 9,136,162 - Huang , et al. September 15, 2	2015-09-15
Self-aligned double spacer patterning process Grant 9,129,906 - Wu , et al. September 8, 2	2015-09-08
Self-aligned double spacer patterning process Grant 9,123,776 - Tsai , et al. September 1, 2	2015-09-01
Spacer-damage-free etching Grant 9,093,386 - Huang , et al. July 28, 2	2015-07-28
Self-Aligned Double Spacer Patterning Process App 20150162205 - Wu; Yung-Hsu ; et al.	2015-06-11
Trench Formation using Horn Shaped Spacer App 20150162238 - Huang; Tsung-Min ; et al.	2015-06-11
Self-Aligned Double Spacer Patterning Process App 20150155198 - Tsai; Cheng-Hsiung ; et al.	2015-06-04
Lithography Using High Selectivity Spacers for Pitch Reduction App 20150155171 - Chang; Yu-Sheng ; et al.	2015-06-04
Integrated Circuits with Reduced Pitch and Line Spacing and Methods of Forming the Same App 20150147882 - Yao; Hsin-Chieh ; et al.	2015-05-28
Spacer-Damage-Free Etching App 20150140811 - Huang; Tsung-Min ; et al.	2015-05-21
Semiconductor Device having Voids and Method of Forming Same App 20150137378 - Wu; Yung-Hsu ; et al.	2015-05-21
Dielectric protection layer as a chemical-mechanical polishing stop layer Grant 8,889,544 - Wu , et al. November 18, 2	2014-11-18
System And Method For Chemical-mechanical Planarization Of A Metal Layer App 20140091477 - Wu; Yung-Hsu ; et al.	2014-04-03
Dielectric Protection Layer As A Chemical-mechanical Polishing Stop Layer App 20120205814 - WU; Yung-Hsu ; et al.	2012-08-16

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