Wu; Xiaoju

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; Xiaoju.The latest application filed is for "high reliability polysilicon components".

Company Profile

12.46.53

Wu; Xiaoju - Dallas TX
Wu; Xiaoju - Yueyang N/A CN
Wu; Xiaoju - Irving TX
Wu; Xiaoju - Yueyuan N/A CN
Wu; Xiaoju - Yueyuan City CN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20220189946 - Salman; Akram A. ; et al.	2022-06-16
High Reliability Polysilicon Components App 20220189949 - Higgins; Robert M. ; et al.	2022-06-16
ESD protection circuit with isolated SCR for negative voltage operation Grant 11,302,688 - Salman , et al. April 12, 2	2022-04-12
High reliability polysilicon components Grant 11,296,075 - Higgins , et al. April 5, 2	2022-04-05
Drain extended transistor Grant 11,152,505 - Sadovnikov , et al. October 19, 2	2021-10-19
Drain extended NMOS transistor Grant 11,094,817 - Wu , et al. August 17, 2	2021-08-17
ESD protection circuit with isolated SCR for negative voltage operation Grant 11,049,852 - Salman , et al. June 29, 2	2021-06-29
Drain centered LDMOS transistor with integrated dummy patterns Grant 10,879,387 - Edwards , et al. December 29, 2	2020-12-29
Drain Extended Nmos Transistor App 20200161471 - Wu; Xiaoju ; et al.	2020-05-21
High Reliability Polysilicon Components App 20200075583 - Higgins; Robert M. ; et al.	2020-03-05
Drain extended NMOS transistor Grant 10,580,890 - Wu , et al.	2020-03-03
Drain Centered Ldmos Transistor With Integrated Dummy Patterns App 20200013890 - Edwards; Henry Litzmann ; et al.	2020-01-09
Drain Extended Transistor App 20200006549 - Sadovnikov; Alexei ; et al.	2020-01-02
Protection Of Drain Extended Transistor Field Oxide App 20200006550 - Todd; James Robert ; et al.	2020-01-02
P-channel DEMOS device Grant 10,505,037 - Tsai , et al. Dec	2019-12-10
Output driver with power down protection Grant 10,498,326 - Wu , et al. De	2019-12-03
Drain centered LDMOS transistor with integrated dummy patterns Grant 10,461,182 - Edwards , et al. Oc	2019-10-29
Semiconductor Device With Extended Electrically-safe Operating Area App 20190214471 - Wu; Xiaoju	2019-07-11
Semiconductor device with extended electrically-safe operating area Grant 10,347,732 - Wu July 9, 2	2019-07-09
Semiconductor device with extended electrically-safe operating area Grant 10,326,014 - Wu	2019-06-18
Drain Extended Nmos Transistor App 20190172946 - Wu; Xiaoju ; et al.	2019-06-06
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20180350795 - Salman; Akram A. ; et al.	2018-12-06
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20180350794 - Salman; Akram A. ; et al.	2018-12-06
MOSFET transistors with robust subthreshold operations Grant 10,090,299 - Wu , et al. October 2, 2	2018-10-02
ESD protection circuit with isolated SCR for negative voltage operation Grant 10,083,951 - Salman , et al. September 25, 2	2018-09-25
Semiconductor Device With Extended Electrically-safe Operating Area App 20180269317 - Wu; Xiaoju	2018-09-20
P-channel Demos Device App 20180197986 - TSAI; CHIN-YU ; et al.	2018-07-12
Semiconductor Device With Extended Electrically-safe Operating Area App 20180190813 - WU; Xiaoju	2018-07-05
Semiconductor device with extended electrically-safe operating area Grant 10,014,405 - Wu July 3, 2	2018-07-03
Mosfet Transistors With Robust Subthreshold Operations App 20180130798 - Wu; Xiaoju ; et al.	2018-05-10
P-channel DEMOS device Grant 9,947,783 - Tsai , et al. April 17, 2	2018-04-17
MOSFET transistors with robust subthreshold operations Grant 9,899,376 - Wu , et al. February 20, 2	2018-02-20
P-channel Demos Device App 20170309744 - TSAI; CHIN-YU ; et al.	2017-10-26
Output Driver With Power Down Protection App 20170257088 - Wu; Xiaoju ; et al.	2017-09-07
MOSFET Transistors with Robust Subthreshold Operations App 20170256537 - Wu; Xiaoju ; et al.	2017-09-07
Catalyst and the preparation process thereof and a process for epoxidising olefin Grant 9,221,039 - Lin , et al. December 29, 2	2015-12-29
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20150294967 - Salman; Akram A. ; et al.	2015-10-15
ESD protection circuit with isolated SCR for negative voltage operation Grant 9,099,523 - Salman , et al. August 4, 2	2015-08-04
Process for producing an alkylene oxide by olefin epoxidation Grant 8,859,791 - Li , et al. October 14, 2	2014-10-14
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20140124828 - Salman; Akram A. ; et al.	2014-05-08
Area-efficient electrically erasable programmable memory cell Grant 8,581,324 - Wu , et al. November 12, 2	2013-11-12
Catalyst, Preparation Method Therefor, And A Method For Epoxidating Olefin App 20130253208 - Lin; Min ; et al.	2013-09-26
Method For Producing Oxidized Olefin Through Olefin Epoxidation App 20130211112 - Li; Hua ; et al.	2013-08-15
Area-efficient Electrically Erasable Programmable Memory Cell App 20120074479 - Wu; Xiaoju ; et al.	2012-03-29
Area-efficient electrically erasable programmable memory cell Grant 8,125,830 - Wu , et al. February 28, 2	2012-02-28
Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom Grant 8,114,744 - Chatterjee , et al. February 14, 2	2012-02-14
Single poly EEPROM without separate control gate nor erase regions Grant 8,067,795 - Mitros , et al. November 29, 2	2011-11-29
Area-efficient Electrically Erasable Programmable Memory Cell App 20110110160 - Wu; Xiaoju ; et al.	2011-05-12
Area-efficient electrically erasable programmable memory cell Grant 7,919,368 - Wu , et al. April 5, 2	2011-04-05
Automatic gain control Grant 7,893,768 - Wang , et al. February 22, 2	2011-02-22
Area-Efficient Electrically Erasable Programmable Memory Cell App 20100302854 - Wu; Xiaoju ; et al.	2010-12-02
Gate Self-aligned Low Noise Jfet App 20100264466 - Wu; Xiaoju ; et al.	2010-10-21
Automatic Gain Control App 20100231299 - Wang; Zhengyu ; et al.	2010-09-16
Method to detect poly residues in LOCOS process Grant 7,785,906 - Wu , et al. August 31, 2	2010-08-31
Methods For Reducing Gate Dielectric Thinning On Trench Isolation Edges And Integrated Circuits Therefrom App 20100164004 - CHATTERJEE; AMITAVA ; et al.	2010-07-01
Gate self aligned low noise JFET Grant 7,745,274 - Wu , et al. June 29, 2	2010-06-29
Body bias to facilitate transistor matching Grant 7,687,856 - Edwards , et al. March 30, 2	2010-03-30
Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device Grant 7,598,547 - Pendharker , et al. October 6, 2	2009-10-06
Simple And Effective Method To Detect Poly Residues In Locos Process App 20090153174 - Wu; Xiaoju ; et al.	2009-06-18
Area efficient differential EEPROM cell with improved data retention and read/write endurance Grant 7,457,173 - Wu November 25, 2	2008-11-25
High Density Capacitor Using Topographic Surface App 20080283966 - Pan; Shanjen ; et al.	2008-11-20
Body Bias To Facilitate Transistor Matching App 20080277731 - Edwards; Henry Litzmann ; et al.	2008-11-13
Single poly EEPROM without separate control gate nor erase regions App 20080225593 - Mitros; Jozef Czeslaw ; et al.	2008-09-18
Gate self aligned low noise JFET App 20080217664 - Wu; Xiaoju ; et al.	2008-09-11
One time programmable EPROM fabrication in STI CMOS technology Grant 7,402,874 - Wu July 22, 2	2008-07-22
Deep buried channel junction field effect transistor (DBCJFET) Grant 7,348,228 - Wu March 25, 2	2008-03-25
EEPROM with etched tunneling window Grant 7,307,309 - Hao , et al. December 11, 2	2007-12-11
Deep buried channel junction field effect transistor (DBCJFET) App 20070275515 - Wu; Xiaoju	2007-11-29
Mitigation of gate oxide thinning in dual gate CMOS process technology App 20070164366 - Wu; Xiaoju ; et al.	2007-07-19
Fabrication of an OTP-EPROM having reduced leakage current Grant 7,244,651 - Wu , et al. July 17, 2	2007-07-17
Low Noise Vertical Variable Gate Control Voltage JFET Device in a BiCMOS Process and Methods to Build this Device App 20070080400 - Pendharker; Sameer P. ; et al.	2007-04-12
Integrated circuit device with a vertical JFET Grant 7,164,160 - Pendharker , et al. January 16, 2	2007-01-16
Area efficient differential EEPROM cell with improved data retention and read/write endurance App 20060262599 - Wu; Xiaoju	2006-11-23
One time programmable EPROM fabrication in STI CMOS technology App 20060244036 - Wu; Xiaoju	2006-11-02
Method for detecting epitaxial (EPI) induced buried layer shifts in semiconductor devices Grant 7,112,953 - Chen , et al. September 26, 2	2006-09-26
Method for manufacturing a MOS transistor having reduced 1/f noise Grant 7,018,880 - Hao , et al. March 28, 2	2006-03-28
Method for detecting EPI induced buried layer shifts in semiconductor devices App 20060038553 - Chen; Xinfen ; et al.	2006-02-23
EEPROM with etched tunneling window App 20050194631 - Hao, Pinghai ; et al.	2005-09-08
Method of manufacturing and structure of semiconductor device (DEMOS) with field oxide structure Grant 6,921,701 - Wu July 26, 2	2005-07-26
Method for manufacturing a metal oxide transistor having reduced 1/f noise App 20050136579 - Hao, Pinghai ; et al.	2005-06-23
Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same Grant 6,885,054 - Wu , et al. April 26, 2	2005-04-26
Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device App 20050067631 - Pendharker, Sameer P. ; et al.	2005-03-31
Method for manufacturing and structure of semiconductor device with polysilicon definition structure Grant 6,870,242 - Wu March 22, 2	2005-03-22
Fabrication of an OTP-EPROM having reduced leakage current App 20040235246 - Wu, Xiaoju ; et al.	2004-11-25
Method for manufacturing and structure of semiconductor device with polysilicon definition structure Grant 6,790,736 - Wu September 14, 2	2004-09-14
Method of manufacturing and structure of semiconductor device with field oxide structure App 20040175892 - Wu, Xiaoju	2004-09-09
Method of manufacturing and structure of semiconductor device with field oxide structure Grant 6,730,962 - Wu May 4, 2	2004-05-04
Method for manufacturing and structure of semiconductor device with polysilicon definition structure App 20040058505 - Wu, Xiaoju	2004-03-25
System for multiple input floating gate structures App 20030141537 - Wu, Xiaoju	2003-07-31
Method of manufacturing and structure of semiconductor device with field oxide structure App 20030109112 - Wu, Xiaoju	2003-06-12
Method for manufacturing and structure of semiconductor device with polysilicon definition structure App 20030100149 - Wu, Xiaoju	2003-05-29
Isolated high voltage MOS transistor App 20020149067 - Mitros, Jozef C. ; et al.	2002-10-17
High density capacitor using topographic surface App 20020084479 - Pan, Shanjen ; et al.	2002-07-04
Electronic circuit with electrical hole isolator App 20020079530 - Wu, Xiaoju ; et al.	2002-06-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.