loadpatents
name:-0.012209892272949
name:-0.020678997039795
name:-0.00089097023010254
Wu; William S. Patent Filings

Wu; William S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; William S..The latest application filed is for "defective block management".

Company Profile
0.17.9
  • Wu; William S. - Cupertino CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Non-volatile memory and method having block management with hot/cold data sorting
Grant 9,176,864 - Gorobets , et al. November 3, 2
2015-11-03
Defective block management
Grant 9,070,449 - Yang , et al. June 30, 2
2015-06-30
Defective Block Management
App 20140321202 - Yang; Nian Niles ;   et al.
2014-10-30
Nonvolatile memory with write cache having flush/eviction methods
Grant 8,700,840 - Paley , et al. April 15, 2
2014-04-15
Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions
App 20120297121 - Gorobets; Sergey Anatolievich ;   et al.
2012-11-22
Non-Volatile Memory and Method Having Block Management with Hot/Cold Data Sorting
App 20120297122 - Gorobets; Sergey Anatolievich ;   et al.
2012-11-22
Non-volatile memory and method with write cache partition management methods
Grant 8,244,960 - Paley , et al. August 14, 2
2012-08-14
Non-volatile memory and method with write cache partitioning
Grant 8,094,500 - Paley , et al. January 10, 2
2012-01-10
Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory
App 20110153912 - Gorobets; Sergey Anatolievich ;   et al.
2011-06-23
Non-Volatile Memory and Method With Write Cache Partitioning
App 20100172180 - Paley; Alexander ;   et al.
2010-07-08
Non-Volatile Memory and Method With Write Cache Partition Management Methods
App 20100174847 - Paley; Alexander ;   et al.
2010-07-08
Nonvolatile Memory With Write Cache Having Flush/Eviction Methods
App 20100174846 - Paley; Alexander ;   et al.
2010-07-08
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
Grant RE40,921 - Wu , et al. September 22, 2
2009-09-22
Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system
Grant 6,598,103 - MacWilliams , et al. July 22, 2
2003-07-22
Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system
App 20020065967 - MacWilliams, Peter D. ;   et al.
2002-05-30
Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
Grant 6,336,159 - MacWilliams , et al. January 1, 2
2002-01-01
Mechanism for delivering interrupt messages
Grant 6,263,397 - Wu , et al. July 17, 2
2001-07-17
High-throughput interface between a system memory controller and a peripheral device
App 20010007999 - Rasmussen, Norman J. ;   et al.
2001-07-12
Method and apparatus for fault on use data error handling
Grant 6,035,436 - Wu , et al. March 7, 2
2000-03-07
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
Grant 5,961,621 - Wu , et al. October 5, 1
1999-10-05
Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
Grant 5,919,254 - Pawlowski , et al. July 6, 1
1999-07-06
Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
Grant 5,906,001 - Wu , et al. May 18, 1
1999-05-18
Adaptively generating timing signals for access to various memory devices based on stored profiles
Grant 5,809,340 - Bertone , et al. September 15, 1
1998-09-15
Symmetric multiprocessing system with unified environment and distributed system functions
Grant 5,522,069 - Bertone , et al. May 28, 1
1996-05-28

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