Wu; Nelson

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; Nelson.The latest application filed is for "pre-silicon chip model of extracted workload inner loop instruction traces".

Company Profile

8.9.7

Wu; Nelson - Austin TX
- Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Pre-silicon Chip Model Of Extracted Workload Inner Loop Instruction Traces App 20210303766 - Wu; Nelson ; et al.	2021-09-30
List insertion in test segments with non-naturally aligned data boundaries Grant 11,094,391 - Dusanapudi , et al. August 17, 2	2021-08-17
Method, system, and apparatus for stress testing memory translation tables Grant 11,061,821 - Dusanapudi , et al. July 13, 2	2021-07-13
System and method for testing processor errors Grant 10,748,637 - Wu , et al. A	2020-08-18
Method, System, And Apparatus For Stress Testing Memory Translation Tables App 20200089621 - Dusanapudi; Manoj ; et al.	2020-03-19
System and Method for Testing Processor Errors App 20200035319A1 -	2020-01-30
Method, system, and apparatus for stress testing memory translation tables Grant 10,521,355 - Dusanapudi , et al. Dec	2019-12-31
Efficient testing of direct memory address translation Grant 10,489,261 - Dusanapudi , et al. Nov	2019-11-26
Efficient testing of direct memory address translation Grant 10,481,991 - Dusanapudi , et al. Nov	2019-11-19
List insertion in test segments with non-naturally aligned data boundaries Grant 10,438,682 - Dusanapudi , et al. O	2019-10-08
List Insertion In Test Segments With Non-naturally Aligned Data Boundaries App 20190287639 - Dusanapudi; Manoj ; et al.	2019-09-19
List Insertion In Test Segments With Non-naturally Aligned Data Boundaries App 20190198132 - Dusanapudi; Manoj ; et al.	2019-06-27
Method, System, And Apparatus For Stress Testing Memory Translation Tables App 20190188146 - Dusanapudi; Manoj ; et al.	2019-06-20
Efficient Testing Of Direct Memory Address Translation App 20190050315 - Dusanapudi; Manoj ; et al.	2019-02-14
Efficient Testing Of Direct Memory Address Translation App 20190050314 - Dusanapudi; Manoj ; et al.	2019-02-14
Efficient testing of direct memory address translation Grant 10,169,186 - Dusanapudi , et al. J	2019-01-01
Efficient testing of direct memory address translation Grant 10,169,185 - Dusanapudi , et al. J	2019-01-01

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