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name:-0.018501996994019
name:-0.00047492980957031
Wu; Lin-June Patent Filings

Wu; Lin-June

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; Lin-June.The latest application filed is for "cmos image sensor big via bonding pad application for aicu process".

Company Profile
0.18.12
  • Wu; Lin-June - Hsin-Chu TW
  • Wu; Lin-June - Hsin-Chu City TW
  • Wu; Lin-June - Hsinchu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
CMOS image sensor big via bonding pad application for AICu process
Grant 8,680,635 - Tseng , et al. March 25, 2
2014-03-25
CMOS image sensor big via bonding pad application for AlCu Process
Grant 8,502,335 - Tseng , et al. August 6, 2
2013-08-06
CMOS Image Sensor Big Via Bonding Pad Application for AICu Process
App 20130134543 - Tseng; Uway ;   et al.
2013-05-30
CMOS image sensor big via bonding pad application for AICu process
Grant 8,344,471 - Tseng , et al. January 1, 2
2013-01-01
CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AlCu PROCESS
App 20110024867 - Tseng; Uway ;   et al.
2011-02-03
CMOS IMAGE SENSOR BIG VIA BONDING PAD APPLICATION FOR AICu PROCESS
App 20110024866 - Tseng; Uway ;   et al.
2011-02-03
Sidewall spacer for semiconductor device and fabrication method thereof
Grant 7,220,650 - Kao , et al. May 22, 2
2007-05-22
Microelectronic fabrication having edge passivated bond pad integrated with option selection device access aperture
Grant 7,067,896 - Wu , et al. June 27, 2
2006-06-27
Method for manufacturing isolation structures in a semiconductor device
App 20050277262 - Tsao, Chang-Sheng ;   et al.
2005-12-15
Sidewall spacer for semiconductor device and fabrication method thereof
App 20050227446 - Kao, Rong-Hui ;   et al.
2005-10-13
Method for implementing poly pre-doping in deep sub-micron process
App 20050118802 - Tsao, Chang-Sheng ;   et al.
2005-06-02
Microelectronic fabrication having edge passivated bond pad integrated with option selection device access aperture
App 20040089916 - Wu, Juei-Kuo ;   et al.
2004-05-13
Tunable threshold voltage of a thick field oxide ESD protection device with a N-field implant
Grant 6,717,220 - Cheng , et al. April 6, 2
2004-04-06
Optical sensor by using tunneling diode
Grant 6,693,317 - Yiu , et al. February 17, 2
2004-02-17
Passivation and planarization process for flip chip packages
Grant 6,667,230 - Chen , et al. December 23, 2
2003-12-23
Novel optical sensor by using tunneling diode
App 20030203525 - Yiu, Ho-Yin ;   et al.
2003-10-30
Method of fabricating borderless contact using graded-stair etch stop layers
Grant 6,635,576 - Liu , et al. October 21, 2
2003-10-21
Dynamic substrate-coupled electrostatic discharging protection circuit
Grant 6,611,028 - Cheng , et al. August 26, 2
2003-08-26
Dynamic substrate-coupled electrostatic discharging protection circuit
App 20030047787 - Cheng, Tao ;   et al.
2003-03-13
Use of a capping layer to reduce particle evolution during sputter pre-clean procedures
Grant 6,531,382 - Cheng , et al. March 11, 2
2003-03-11
Tunable threshold voltage of a thick field oxide ESD protection device with a N-field implant
App 20030017673 - Cheng, Tao ;   et al.
2003-01-23
Passivation and planarization process for flip chip packages
App 20030013291 - Chen, Dian-Hau ;   et al.
2003-01-16
Dynamic substrate-coupled electrostatic discharging protection circuit
Grant 6,479,872 - Cheng , et al. November 12, 2
2002-11-12
Novel optical sensor by using tunneling diode
App 20010039067 - Yiu, Ho-Yin ;   et al.
2001-11-08
Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process
Grant 6,077,746 - You , et al. June 20, 2
2000-06-20
Stress buffered bond pad and method of making
Grant 5,942,800 - Yiu , et al. August 24, 1
1999-08-24
Method of protecting an alignment mark in a semiconductor manufacturing process with CMP
Grant 5,801,090 - Wu , et al. September 1, 1
1998-09-01
Technique for the removal of residual spin-on-glass (SOG) after full SOG etchback
Grant 5,747,381 - Wu , et al. May 5, 1
1998-05-05
Method for selectively depositing silicon oxide spacer layers
Grant 5,518,959 - Jang , et al. May 21, 1
1996-05-21

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