loadpatents
name:-0.0083479881286621
name:-0.0091230869293213
name:-0.0017168521881104
Wu; Kun-Cheng Patent Filings

Wu; Kun-Cheng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; Kun-Cheng.The latest application filed is for "methodology and system for setup/hold time characterization of analog ip".

Company Profile
2.9.5
  • Wu; Kun-Cheng - Changhua TW
  • Wu; Kun-Cheng - Hsinchu TW
  • Wu; Kun-Cheng - Hsin-Chu City TW
  • Wu; Kun-Cheng - Taiwan TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Power-saving luminous basketball hoop set
Grant 10,857,439 - Yang , et al. December 8, 2
2020-12-08
Basketball shooting training device
Grant 10,814,199 - Wu , et al. October 27, 2
2020-10-27
Methodology and system for setup/hold time characterization of analog IP
Grant 7,596,772 - Chen , et al. September 29, 2
2009-09-29
Methodology And System For Setup/hold Time Characterization Of Analog Ip
App 20080141198 - Chen; Hanping ;   et al.
2008-06-12
Method for reducing standard delay format file size
Grant 7,290,231 - Wu , et al. October 30, 2
2007-10-30
Method For Static Power Characterization Of An Integrated Circuit
App 20070214438 - Chen; Peter H. Chen Hanping ;   et al.
2007-09-13
Method of generating protected standard delay format file
Grant 7,131,079 - Wu , et al. October 31, 2
2006-10-31
Method of generating protected standard delay format file
App 20050251764 - Wu, Kun-Cheng ;   et al.
2005-11-10
[method For Reducing Standard Delay Format File Size]
App 20050177806 - Wu, Kun-Cheng ;   et al.
2005-08-11
Apparatus for low-power, high performance, and cycle accurate test simulation
App 20020075058 - Hwang, Chi-Yi ;   et al.
2002-06-20
Intermediate instruction execution processor which resolves symbolic references without modifying intermediate instruction code
Grant 6,382,846 - Lai , et al. May 7, 2
2002-05-07
System for packing variable length instructions into fixed length blocks with indications of instruction beginning, ending, and offset within block
Grant 6,035,387 - Hsu , et al. March 7, 2
2000-03-07
Branch prediction and fetch mechanism for variable length instruction, superscalar pipelined processor
Grant 5,948,100 - Hsu , et al. September 7, 1
1999-09-07

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