Wu; Juing-Yi
Patent Applications and Registrations
Patent applications and USPTO patent grants for Wu; Juing-Yi.The latest application filed is for "different scaling ratio in feol / mol/ beol".
Company Profile
9.22.23
- Wu; Juing-Yi - Hsinchu TW
- Wu; Juing-Yi - Hsinchu City TW
- Wu; Juing-Yi - Hsin-Chu TW
- Wu; Juing-Yi - Chang Hua TW
Patent Activity
| Patent | Date |
|---|---|
| Cell layout and structure Grant 11,281,835 - Hsieh , et al. March 22, 2 | 2022-03-22 |
| Different Scaling Ratio In Feol / Mol/ Beol App 20220068812 - Lee; Liang-Yao ; et al. | 2022-03-03 |
| Different scaling ratio in FEOL / MOL/ BEOL Grant 11,152,303 - Lee , et al. October 19, 2 | 2021-10-19 |
| Conductive line patterning Grant 10,998,304 - Liu , et al. May 4, 2 | 2021-05-04 |
| Cell Layout and Structure App 20200257842 - Hsieh; Tung-Heng ; et al. | 2020-08-13 |
| Cell layout and structure Grant 10,664,639 - Hsieh , et al. | 2020-05-26 |
| Different Scaling Ratio In Feol / Mol/ Beol App 20190287905 - Lee; Liang-Yao ; et al. | 2019-09-19 |
| Conductive Line Patterning App 20190244950 - Liu; Ru-Gun ; et al. | 2019-08-08 |
| Semiconductor device and manufacturing method thereof Grant 10,366,900 - Wu , et al. July 30, 2 | 2019-07-30 |
| Different scaling ratio in FEOL/ MOL/ BEOL Grant 10,325,849 - Lee , et al. | 2019-06-18 |
| Mask optimization for multi-layer contacts Grant 10,283,495 - Liu , et al. | 2019-05-07 |
| Conductive line patterning Grant 10,269,785 - Liu , et al. | 2019-04-23 |
| Cell Layout and Structure App 20180253522 - Hsieh; Tung-Heng ; et al. | 2018-09-06 |
| Cell layout and structure Grant 9,984,191 - Hsieh , et al. May 29, 2 | 2018-05-29 |
| Semiconductor Device And Manufacturing Method Thereof App 20170278717 - WU; Juing-Yi ; et al. | 2017-09-28 |
| Method for preventing photoresist corner rounding effects Grant 9,746,783 - Lee , et al. August 29, 2 | 2017-08-29 |
| Implant region definition Grant 9,637,818 - Wu , et al. May 2, 2 | 2017-05-02 |
| Conductive Line Patterning App 20170025401 - Liu; Ru-Gun ; et al. | 2017-01-26 |
| Semiconductor device having a metal gate Grant 9,508,791 - Tsai , et al. November 29, 2 | 2016-11-29 |
| Conductive line patterning Grant 9,472,501 - Liu , et al. October 18, 2 | 2016-10-18 |
| Mask Optimization For Multi-Layer Contacts App 20160293590 - Liu; Ru-Gun ; et al. | 2016-10-06 |
| Mask optimization for multi-layer contacts Grant 9,391,056 - Liu , et al. July 12, 2 | 2016-07-12 |
| Different Scaling Ratio In Feol / Mol/ Beol App 20160155704 - Lee; Liang-Yao ; et al. | 2016-06-02 |
| Semiconductor Device Having A Metal Gate App 20160133693 - Tsai; Tsung-Chieh ; et al. | 2016-05-12 |
| Different scaling ratio in FEOL / MOL/ BEOL Grant 9,292,649 - Lee , et al. March 22, 2 | 2016-03-22 |
| Cell Layout and Structure App 20160063166 - Hsieh; Tung-Heng ; et al. | 2016-03-03 |
| Conductive Line Patterning App 20150333002 - Liu; Ru-Gun ; et al. | 2015-11-19 |
| Implant Region Definition App 20150322565 - Wu; Juing-Yi ; et al. | 2015-11-12 |
| Conductive line patterning Grant 9,136,168 - Liu , et al. September 15, 2 | 2015-09-15 |
| Implant region definition Grant 9,087,773 - Wu , et al. July 21, 2 | 2015-07-21 |
| Method, system and software for accessing design rules and library of design features while designing semiconductor device layout Grant 9,047,437 - Chen , et al. June 2, 2 | 2015-06-02 |
| Different Scaling Ratio In Feol / Mol/ Beol App 20150143319 - Lee; Liang-Yao ; et al. | 2015-05-21 |
| Implant Region Definition App 20150072480 - Wu; Juing-Yi ; et al. | 2015-03-12 |
| Mask Optimization for Multi-Layer Contacts App 20150048457 - Liu; Ru-Gun ; et al. | 2015-02-19 |
| Conductive Line Patterning App 20150001734 - Liu; Ru-Gun ; et al. | 2015-01-01 |
| Method, System And Software For Accessing Design Rules And Library Of Design Features While Designing Semiconductor Device Layout App 20140282294 - CHEN; Chin-An ; et al. | 2014-09-18 |
| Method, system and software for accessing design rules and library of design features while designing semiconductor device layout Grant 8,769,475 - Chen , et al. July 1, 2 | 2014-07-01 |
| Method, System And Software For Accessing Design Rules And Library Of Design Features While Designing Semiconductor Device Layout App 20130111418 - Chen; Chin-An ; et al. | 2013-05-02 |
| Electrostatic discharge protector for an integrated circuit Grant 7,309,897 - Yu , et al. December 18, 2 | 2007-12-18 |
| Electrostatic Discharge Protector For An Integrated Circuit App 20070241406 - Yu; Kuo-Feng ; et al. | 2007-10-18 |
| Mixed implantation on polysilicon fuse for CMOS technology App 20050258505 - Wu, Juing-Yi ; et al. | 2005-11-24 |
| Partially photoexposed positive photoresist layer blocking method for regio-selectively processing a microelectronic layer Grant 6,936,408 - Liao , et al. August 30, 2 | 2005-08-30 |
| Partially photoexposed positive photoresist layer blocking method for regio-selectively processing a microelectronic layer App 20040013981 - Liao, Yong-Shun ; et al. | 2004-01-22 |
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