WU; Hanming

Patent Applications and Registrations

Patent applications and USPTO patent grants for WU; Hanming.The latest application filed is for "preparation method for accurate pattern of integrated circuit".

Company Profile

0.18.21

WU; Hanming - Beijing CN
Wu; Hanming - Taipei TW
Wu; Hanming - Shanghai CN
Wu; Hanming - Fujian CN
Wu; Hanming - Taipei City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Preparation Method For Accurate Pattern Of Integrated Circuit App 20220051903 - WU; Hanming	2022-02-17
Computing device for data managing and decision making Grant 10,552,407 - Chen , et al. Fe	2020-02-04
TSV interconnect structure and manufacturing method thereof Grant 10,515,892 - Bu , et al. Dec	2019-12-24
Semiconductor device, related manufacturing method, and related electronic device Grant 10,128,117 - Wang , et al. November 13, 2	2018-11-13
Semiconductor Device, Related Manufacturing Method, And Related Electronic Device App 20180012765 - WANG; Wenbo ; et al.	2018-01-11
Semiconductor device, related manufacturing method, and related electronic device Grant 9,799,525 - Wang , et al. October 24, 2	2017-10-24
Grill device Grant 9,648,985 - Huang , et al. May 16, 2	2017-05-16
Fin-type field effect transistor and manufacturing method thereof Grant 9,590,031 - Xiao , et al. March 7, 2	2017-03-07
Computing Device for Data Managing and Decision Making App 20160350361 - Chen; Chikuan ; et al.	2016-12-01
Method For Fabricating A Quasi-soi Source-drain Multi-gate Device App 20160247726 - HUANG; Ru ; et al.	2016-08-25
Semiconductor Device, Related Manufacturing Method, And Related Electronic Device App 20160240670 - WANG; Wenbo ; et al.	2016-08-18
Method for fabricating quasi-SOI source/drain field effect transistor device Grant 9,349,588 - Huang , et al. May 24, 2	2016-05-24
Method For Fabricating Quasi-soi Source/drain Field Effect Transistor Device App 20160118245 - Huang; Ru ; et al.	2016-04-28
Grill Device App 20150320258 - HUANG; Zhenshan ; et al.	2015-11-12
Fin-type Field Effect Transistor And Manufacturing Method Thereof App 20150279933 - XIAO; Deyuan ; et al.	2015-10-01
Method for dual energy implantation for ultra-shallow junction formation of MOS devices Grant 9,024,281 - Wu , et al. May 5, 2	2015-05-05
Tsv Interconnect Structure And Manufacturing Method Thereof App 20140374916 - BU; WEIHAI ; et al.	2014-12-25
CMOS devices and fabrication method Grant 8,901,675 - Bu , et al. December 2, 2	2014-12-02
Cmos Devices And Fabrication Method App 20140015064 - BU; WEIHAI ; et al.	2014-01-16
Method For Dual Energy Implantation For Ultra-shallow Junction Formation Of Mos Devices App 20130264491 - Wu; Hanming ; et al.	2013-10-10
Silicon germanium and polysilicon gate structure for strained silicon transistors Grant 8,551,831 - Gao , et al. October 8, 2	2013-10-08
Method for dual energy implantation for ultra-shallow junction formation of MOS devices Grant 8,466,050 - Wu , et al. June 18, 2	2013-06-18
Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors Grant 8,106,423 - Wu , et al. January 31, 2	2012-01-31
Method For Dual Energy Implantation For Ultra-shallow Junction Formation Of Mos Devices App 20110143512 - WU; HANMING ; et al.	2011-06-16
Metal hard mask method and structure for strained silicon MOS transistors Grant 7,709,336 - Ning , et al. May 4, 2	2010-05-04
Method and structure for second spacer formation for strained silicon MOS transistors Grant 7,591,659 - Chen , et al. September 22, 2	2009-09-22
Etching method and structure using a hard mask for strained silicon MOS transistors Grant 7,557,000 - Chen , et al. July 7, 2	2009-07-07
Silicon Germanium and Polysilicon Gate Structure for Strained Silicon Transistors App 20090152599 - Gao; Da Wei ; et al.	2009-06-18
Method and structure using a pure silicon dioxide hardmask for gate pattering for strained silicon MOS transistors App 20090065805 - Wu; Hanming ; et al.	2009-03-12
Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors Grant 7,425,488 - Wu , et al. September 16, 2	2008-09-16
Etching Method And Structure In A Silicon Recess For Subsequent Epitaxial Growth For Strained Silicon Mos Transistors App 20080173941 - Zhu; Bei ; et al.	2008-07-24
Etching Method And Structure Using A Hard Mask For Strained Silicon Mos Transistors App 20080119032 - Chen; John ; et al.	2008-05-22
Pulsed Plasma Etching Method And Apparatus App 20080081483 - Wu; Hanming	2008-04-03
In-situ doped silicon germanium and silicon carbide source drain region for strained silicon CMOS transistors App 20070196992 - Xiang; Mo Hong ; et al.	2007-08-23
Method and structure for second spacer formation for strained silicon MOS transistors App 20070077716 - Chen; John ; et al.	2007-04-05
Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors App 20070063221 - Wu; Hanming ; et al.	2007-03-22
Metal hard mask method and structure for strained silicon MOS transistors App 20060194395 - Ning; Xian J. ; et al.	2006-08-31

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