Wu; David Donggang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; David Donggang.The latest application filed is for "semiconductor device with transistor-based fuses and related programming method".

Company Profile

0.11.5

Wu; David Donggang - Austin TX US
Wu; David Donggang - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electronic device and method of biasing Grant 8,687,417 - Li , et al. April 1, 2	2014-04-01
Semiconductor device with transistor-based fuses and related programming method Grant 8,050,077 - Li , et al. November 1, 2	2011-11-01
Semiconductor Device With Transistor-based Fuses And Related Programming Method App 20100214008 - LI; Ruigang ; et al.	2010-08-26
Distinguishing between dopant and line width variation components Grant 7,582,493 - Sultan , et al. September 1, 2	2009-09-01
Electronic Device And Method Of Biasing App 20090090969 - Li; Ruigang ; et al.	2009-04-09
Distinguishing Between Dopant and Line Width Variation Components App 20080085570 - Sultan; Akif ; et al.	2008-04-10
Method of forming a gate electrode on a semiconductor device and a device incorporating same Grant 7,087,509 - Roche , et al. August 8, 2	2006-08-08
Test structure for high precision analysis of a semiconductor Grant 6,872,583 - Wu March 29, 2	2005-03-29
Method of forming resistive structures App 20040235258 - Wu, David Donggang ; et al.	2004-11-25
Method of forming a hard mask for halo implants Grant 6,624,035 - Luning , et al. September 23, 2	2003-09-23
Salicide block for silicon-on-insulator (SOI) applications Grant 6,586,311 - Wu July 1, 2	2003-07-01
Salicide block for silicon-on-insulator (SOI) applications App 20020158291 - Wu, David Donggang	2002-10-31
Method for forming vertical profile of polysilicon gate electrodes Grant 6,391,751 - Wu , et al. May 21, 2	2002-05-21
Method of forming a semiconductor device with source/drain regions having a deep vertical junction Grant 6,368,926 - Wu April 9, 2	2002-04-09
Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance Grant 5,925,914 - Jiang , et al. July 20, 1	1999-07-20

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