Wu; Chung-Hsiao R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wu; Chung-Hsiao R..The latest application filed is for "system memory board subsystem using dram with stacked dedicated high speed point to point links".

Company Profile

0.12.11

Wu; Chung-Hsiao R. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System memory board subsystem using DRAM with stacked dedicated high speed point to point links Grant 7,409,491 - Doblar , et al. August 5, 2	2008-08-05
Dynamic memory throttling for power and thermal limitations Grant 7,352,641 - Wu April 1, 2	2008-04-01
Clock distribution architecture with spread spectrum Grant 7,334,149 - Wu February 19, 2	2008-02-19
Variable memory refresh rate for DRAM Grant 7,233,538 - Wu , et al. June 19, 2	2007-06-19
System memory board subsystem using dram with stacked dedicated high speed point to point links App 20070136537 - Doblar; Drew G. ; et al.	2007-06-14
Dynamic memory throttling for power and thermal limitations Grant 7,064,994 - Wu June 20, 2	2006-06-20
Clock distribution architecture having clock and power failure protection Grant 7,051,235 - Wu May 23, 2	2006-05-23
Redundant clock synthesizer Grant 7,043,655 - Wu May 9, 2	2006-05-09
Memory subsystem including memory modules having multiple banks Grant 6,996,686 - Doblar , et al. February 7, 2	2006-02-07
Circuit topology for high-speed memory access Grant 6,930,904 - Wu August 16, 2	2005-08-16
Double data rate (DDR) data strobe receiver Grant 6,853,594 - Wu , et al. February 8, 2	2005-02-08
Double Data Rate (ddr) Data Strobe Receiver App 20050018494 - Wu, Chung-Hsiao R. ; et al.	2005-01-27
Memory integrated circuit including an error detection mechanism for detecting errors in address and control signals App 20040237001 - Schulz, Jurgen M. ; et al.	2004-11-25
Memory subsystem including memory modules having multiple banks App 20040123016 - Doblar, Drew G. ; et al.	2004-06-24
Circuit topology for high speed memory access App 20040100812 - Wu, Chung-Hsiao R.	2004-05-27
Redundant clock synthesizer App 20040088597 - Wu, Chung-Hsiao R.	2004-05-06
Circuit topology for clock signal distribution topology App 20040057330 - Wu, Chung-Hsiao R.	2004-03-25
Clock distribution architecture having clock and power failure protection App 20040044922 - Wu, Chung-Hsiao R.	2004-03-04
Bi-directional output buffer Grant 6,690,191 - Wu , et al. February 10, 2	2004-02-10
Bi-directional output buffer App 20030117172 - Wu, Chung-Hsiao R. ; et al.	2003-06-26
Apparatus For On-chip Reference Voltage Generator For Receivers In High Speed Single-ended Data Link App 20030034829 - Wu, Chung-Hsiao R. ; et al.	2003-02-20
Data strobe receiver Grant 6,512,704 - Wu , et al. January 28, 2	2003-01-28
Compensation Circuit For Low Phase Offset For Phase-locked Loops App 20010013800 - WU, CHUNG-HSIAO R. ; et al.	2001-08-16

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