Wristers; Derick J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wristers; Derick J..The latest application filed is for "method of forming doped regions in the bulk substrate of an soi substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same".

Company Profile

0.94.14

Wristers; Derick J. - Bee Caves TX
Wristers; Derick J - Bee Caves TX
Wristers; Derick J. - Austin TX
Wristers; Derick J. - both of Austin all of

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate Grant 7,544,999 - Wei , et al. June 9, 2	2009-06-09
Transistors with controllable threshold voltages, and various methods of making and operating same Grant 7,432,136 - Fuselier , et al. October 7, 2	2008-10-07
Strained-silicon device with different silicon thicknesses Grant 7,417,250 - Buller , et al. August 26, 2	2008-08-26
Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same Grant 7,335,568 - Wristers , et al. February 26, 2	2008-02-26
Selective P-channel V.sub.T adjustment in SiGe system for leakage optimization Grant 7,253,045 - Wristers , et al. August 7, 2	2007-08-07
Biased, triple-well fully depleted SOI structure Grant 7,180,136 - Wei , et al. February 20, 2	2007-02-20
Method Of Forming Doped Regions In The Bulk Substrate Of An Soi Substrate To Control The Operational Characteristics Of Transistors Formed Thereabove, And An Integrated Circuit Device Comprising Same App 20070015322 - Wristers; Derick J. ; et al.	2007-01-18
Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same Grant 7,129,142 - Wristers , et al. October 31, 2	2006-10-31
Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites Grant 6,979,878 - Gardner , et al. December 27, 2	2005-12-27
Strained-silicon devices with different silicon thicknesses Grant 6,936,506 - Buller , et al. August 30, 2	2005-08-30
Biased, triple-well fully depleted SOI structure App 20050184341 - Wei, Andy C. ; et al.	2005-08-25
Biased, triple-well fully depleted SOI structure, and various methods of making and operating same Grant 6,919,236 - Wei , et al. July 19, 2	2005-07-19
SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate App 20050151133 - Wei, Andy C. ; et al.	2005-07-14
Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate Grant 6,884,702 - Wei , et al. April 26, 2	2005-04-26
Fully-depleted SOI device Grant 6,876,037 - Wei , et al. April 5, 2	2005-04-05
Linewidth measurement structure with embedded scatterometry structure Grant 6,822,260 - Nariman , et al. November 23, 2	2004-11-23
Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same App 20040219761 - Fuselier, Mark B. ; et al.	2004-11-04
Polysilicon linewidth measurement structure with embedded transistor Grant 6,812,506 - Nariman , et al. November 2, 2	2004-11-02
Ring oscillator with embedded scatterometry grate array Grant 6,801,096 - Nariman , et al. October 5, 2	2004-10-05
Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions App 20040169227 - Wei, Andy C. ; et al.	2004-09-02
Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions Grant 6,780,686 - Wei , et al. August 24, 2	2004-08-24
Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents Grant 6,764,908 - Kadosh , et al. July 20, 2	2004-07-20
Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same Grant 6,737,332 - Fuselier , et al. May 18, 2	2004-05-18
Formation of ultra-shallow depth source/drain extensions for MOS transistors Grant 6,727,136 - Buller , et al. April 27, 2	2004-04-27
Electrically programmed MOS transistor source/drain series resistance Grant 6,727,534 - Buller , et al. April 27, 2	2004-04-27
Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer Grant 6,707,106 - Wristers , et al. March 16, 2	2004-03-16
Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate Grant 6,689,671 - Yu , et al. February 10, 2	2004-02-10
Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same App 20030228722 - Wristers, Derick J. ; et al.	2003-12-11
Tri-level segmented control transistor and fabrication method Grant 6,661,057 - Dawson , et al. December 9, 2	2003-12-09
Method of making an soi semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate App 20030223258 - Wei, Andy C. ; et al.	2003-12-04
Transistors with controllable threshold voltages, and various methods of making and operating same App 20030207504 - Fuselier, Mark B. ; et al.	2003-11-06
Doping Methods For Fully-depleted Soi Structures, And Device Comprising The Resulting Doped Regions App 20030178678 - Wei, Andy C. ; et al.	2003-09-25
Biased, triple-well fully depleted SOI structure, and various methods of making and operating same App 20030178622 - Wei, Andy C. ; et al.	2003-09-25
Tilted counter-doped implant to sharpen halo profile Grant 6,589,847 - Kadosh , et al. July 8, 2	2003-07-08
Photolithographic system including light filter that compensates for lens error Grant 6,552,776 - Wristers , et al. April 22, 2	2003-04-22
Dopant diffusion-retarding barrier region formed within polysilicon gate layer Grant 6,380,055 - Gardner , et al. April 30, 2	2002-04-30
Angled halo implant tailoring using implant mask Grant 6,372,587 - Cheek , et al. April 16, 2	2002-04-16
Igfet With Silicide Contact On Ultra-thin Gate App 20020003273 - DAWSON, ROBERT ; et al.	2002-01-10
Dopant Diffusion-retarding Barrier Region Formed Within Polysilicon Gate Layer App 20020004294 - GARDNER, MARK I. ; et al.	2002-01-10
Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process Grant 6,323,519 - Gardner , et al. November 27, 2	2001-11-27
Method Of Making An Igfet Using Solid Phase Diffusion To Dope The Gate, Source And Drain App 20010039094 - WRISTERS, DERICK J. ; et al.	2001-11-08
Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions Grant 6,300,205 - Fulford , et al. October 9, 2	2001-10-09
High Density Memory Cell Assembly And Methods App 20010020716 - GARDNER, MARK I. ; et al.	2001-09-13
Multiple split gate semiconductor device and fabrication method Grant 6,259,142 - Dawson , et al. July 10, 2	2001-07-10
Integrated circuit gate conductor which uses layered spacers to produce a graded junction Grant 6,258,680 - Fulford, Jr. , et al. July 10, 2	2001-07-10
Method for forming a retrograde impurity profile Grant 6,245,649 - Buller , et al. June 12, 2	2001-06-12
Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion Grant 6,225,151 - Gardner , et al. May 1, 2	2001-05-01
Trench transistor with insulative spacers Grant 6,201,278 - Gardner , et al. March 13, 2	2001-03-13
Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls Grant 6,197,645 - Michael , et al. March 6, 2	2001-03-06
Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions Grant 6,187,620 - Fulford, Jr. , et al. February 13, 2	2001-02-13
Method of forming an insulated-gate field-effect transistor with metal spacers Grant 6,188,114 - Gardner , et al. February 13, 2	2001-02-13
High performance transistor fabricated on a dielectric film and method of making same Grant 6,188,107 - Gardner , et al. February 13, 2	2001-02-13
Method of fabricating a transistor with a dielectric underlayer and device incorporating same Grant 6,162,688 - Gardner , et al. December 19, 2	2000-12-19
Multi-layer gate conductor having a diffusion barrier in the bottom layer Grant 6,160,300 - Gardner , et al. December 12, 2	2000-12-12
Multilevel transistor formation employing a local substrate formed within a shallow trench Grant 6,150,695 - Gardner , et al. November 21, 2	2000-11-21
Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance Grant 6,146,978 - Michael , et al. November 14, 2	2000-11-14
Transistor with integrated poly/metal gate electrode Grant 6,118,163 - Gardner , et al. September 12, 2	2000-09-12
Semiconductor device with vertical halo region and methods of manufacture Grant 6,114,211 - Fulford , et al. September 5, 2	2000-09-05
CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions Grant 6,107,130 - Fulford, Jr. , et al. August 22, 2	2000-08-22
Multiple spacer formation/removal technique for forming a graded junction Grant 6,104,063 - Fulford, Jr. , et al. August 15, 2	2000-08-15
Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication Grant 6,103,559 - Gardner , et al. August 15, 2	2000-08-15
Method of forming trench transistor with insulative spacers Grant 6,100,146 - Gardner , et al. August 8, 2	2000-08-08
Method of forming a semiconductor device having narrow gate electrode Grant 6,096,615 - Gardner , et al. August 1, 2	2000-08-01
Method of making an IGFET and a protected resistor with reduced processing steps Grant 6,096,591 - Gardner , et al. August 1, 2	2000-08-01
Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls Grant 6,087,706 - Dawson , et al. July 11, 2	2000-07-11
Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers Grant 6,074,906 - Cheek , et al. June 13, 2	2000-06-13
Method of making NMOS and PMOS devices with reduced masking steps Grant 6,060,345 - Hause , et al. May 9, 2	2000-05-09
Transistor having a barrier layer below a high permittivity gate dielectric Grant 6,051,865 - Gardner , et al. April 18, 2	2000-04-18
Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate Grant 6,051,459 - Gardner , et al. April 18, 2	2000-04-18
Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device Grant 6,030,752 - Fulford, Jr. , et al. February 29, 2	2000-02-29
Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties Grant 6,018,179 - Gardner , et al. January 25, 2	2000-01-25
Method of making high performance MOSFET with integrated poly/metal gate electrode Grant 5,994,193 - Gardner , et al. November 30, 1	1999-11-30
Stacked poly-oxide-poly gate for improved silicide formation Grant 5,981,365 - Cheek , et al. November 9, 1	1999-11-09
Method of making a self-aligned disposable gate electrode for advanced CMOS design Grant 5,976,924 - Gardner , et al. November 2, 1	1999-11-02
Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device Grant 5,976,956 - Gardner , et al. November 2, 1	1999-11-02
MOSFET device with an amorphized source Grant 5,969,407 - Gardner , et al. October 19, 1	1999-10-19
Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor Grant 5,959,333 - Gardner , et al. September 28, 1	1999-09-28
Method of forming a conductive plug in an interlevel dielectric Grant 5,935,766 - Cheek , et al. August 10, 1	1999-08-10
Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls Grant 5,937,299 - Michael , et al. August 10, 1	1999-08-10
Method of making an IGFET with a multilevel gate Grant 5,930,634 - Hause , et al. July 27, 1	1999-07-27
Transistor with buried insulative layer beneath the channel region Grant 5,930,642 - Moore , et al. July 27, 1	1999-07-27
Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects Grant 5,923,983 - Fulford, Jr. , et al. July 13, 1	1999-07-13
Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size Grant 5,918,126 - Fulford, Jr. , et al. June 29, 1	1999-06-29
Method of channel doping using diffusion from implanted polysilicon Grant 5,918,129 - Fulford, Jr. , et al. June 29, 1	1999-06-29
Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device Grant 5,899,732 - Gardner , et al. May 4, 1	1999-05-04
Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure Grant 5,891,787 - Gardner , et al. April 6, 1	1999-04-06
Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric Grant 5,885,877 - Gardner , et al. March 23, 1	1999-03-23
Method of making an igfet with selectively doped multilevel polysilicon gate Grant 5,885,887 - Hause , et al. March 23, 1	1999-03-23
Method of forming an insulated-gate field-effect transistor with metal spacers Grant 5,877,058 - Gardner , et al. March 2, 1	1999-03-02
Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals Grant 5,877,050 - Gardner , et al. March 2, 1	1999-03-02
CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof Grant 5,874,343 - Fulford, Jr. , et al. February 23, 1	1999-02-23
Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions Grant 5,869,866 - Fulford, Jr. , et al. February 9, 1	1999-02-09
CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions Grant 5,869,879 - Fulford, Jr. , et al. February 9, 1	1999-02-09
IGFET method of forming with silicide contact on ultra-thin gate Grant 5,851,891 - Dawson , et al. December 22, 1	1998-12-22
Integrated circuit gate conductor which uses layered spacers to produce a graded junction Grant 5,847,428 - Fulford, Jr. , et al. December 8, 1	1998-12-08
CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof Grant 5,844,276 - Fulford, Jr. , et al. December 1, 1	1998-12-01
Individually controllable radiation sources for providing an image pattern in a photolithographic system Grant 5,840,451 - Moore , et al. November 24, 1	1998-11-24
Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region Grant 5,831,306 - Gardner , et al. November 3, 1	1998-11-03
Method of making NMOS and devices with sequentially formed gates having different gate lengths Grant 5,827,761 - Fulford, Jr. , et al. October 27, 1	1998-10-27
Method of forming a gate electrode for an IGFET Grant 5,801,088 - Gardner , et al. September 1, 1	1998-09-01
Method of forming trench transistor with metal spacers Grant 5,801,075 - Gardner , et al. September 1, 1	1998-09-01
Trench transistor in combination with trench array Grant 5,796,143 - Fulford, Jr. , et al. August 18, 1	1998-08-18
MOSFET device with an amorphized source and fabrication method thereof Grant 5,770,485 - Gardner , et al. June 23, 1	1998-06-23
Inspection of lens error associated with lens heating in a photolithographic system Grant 5,723,238 - Moore , et al. March 3, 1	1998-03-03
Method of forming a shallow junction by diffusion from a silicon-based spacer Grant 5,710,054 - Gardner , et al. January 20, 1	1998-01-20
Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants Grant 5,679,585 - Gardner , et al. October 21, 1	1997-10-21
Method for fabrication of a non-symmetrical transistor Grant 5,672,531 - Gardner , et al. September 30, 1	1997-09-30
Semiconductor wafer with enhanced pre-process denudation and process-induced gettering Grant 5,445,975 - Gardner , et al. August 29, 1	1995-08-29