Wottreng; Andrew H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wottreng; Andrew H..The latest application filed is for "methods and apparatus for handling a cache miss".

Company Profile

0.17.15

Wottreng; Andrew H. - NW Rochester MN US
Wottreng; Andrew H. - Rochester MN
Wottreng; Andrew H. - Brainerd MN
Wottreng; Andrew H. - Byron MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and apparatus for handling a cache miss Grant 8,589,630 - Irish , et al. November 19, 2	2013-11-19
Methods and apparatus for handling a cache miss Grant 8,327,075 - Irish , et al. December 4, 2	2012-12-04
Methods And Apparatus For Handling A Cache Miss App 20120272009 - Irish; John D. ; et al.	2012-10-25
Loading entries into a TLB in hardware via indirect TLB entries Grant 8,296,547 - Heil , et al. October 23, 2	2012-10-23
Mechanisms for priority control in resource allocation Grant 8,180,941 - Chen , et al. May 15, 2	2012-05-15
Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations Grant 8,127,082 - McBride , et al. February 28, 2	2012-02-28
Method to bypass cache levels in a cache coherent system Grant 8,108,617 - Heil , et al. January 31, 2	2012-01-31
Mechanisms for Priority Control in Resource Allocation App 20100146512 - Chen; Wen-Tzer T. ; et al.	2010-06-10
I/O address translation method for specifying a relaxed ordering for I/O accesses Grant 7,721,023 - Irish , et al. May 18, 2	2010-05-18
Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes Grant 7,716,423 - Irish , et al. May 11, 2	2010-05-11
Loading Entries Into A Tlb In Hardware Via Indirect Tlb Entries App 20100058026 - Heil; Timothy H. ; et al.	2010-03-04
Priority control in resource allocation for low request rate, latency-sensitive units Grant 7,631,131 - Chen , et al. December 8, 2	2009-12-08
Method to Bypass Cache Levels in a Cache Coherent System App 20090204769 - Heil; Timothy H. ; et al.	2009-08-13
Handling Concurrent Address Translation Cache Misses And Hits Under Those Misses While Maintaining Command Order App 20090187695 - Irish; John D. ; et al.	2009-07-23
Handling concurrent address translation cache misses and hits under those misses while maintaining command order Grant 7,539,840 - Irish , et al. May 26, 2	2009-05-26
Invalidating multiple address cache entries Grant 7,472,227 - McBride , et al. December 30, 2	2008-12-30
Method and Apparatus for Handling Concurrent Address Translation Cache Misses and Hits Under Those Misses While Maintaining Command Order App 20070283121 - Irish; John D. ; et al.	2007-12-06
Hardware Assisted Exception for Software Miss Handling of an I/O Address Translation Cache Miss App 20070260754 - Irish; John D. ; et al.	2007-11-08
Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes App 20070186046 - Irish; John D. ; et al.	2007-08-09
Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations App 20070180195 - McBride; Chad B. ; et al.	2007-08-02
I/O address translation blocking in a secure system during power-on-reset App 20070180269 - Irish; John D. ; et al.	2007-08-02
Methods and apparatus for handling a cache miss App 20070136532 - Irish; John D. ; et al.	2007-06-14
I/O address translation apparatus and method for specifying a relaxed ordering for I/O accesses App 20070130372 - Irish; John D. ; et al.	2007-06-07
Priority control in resource allocation for low request rate, latency-sensitive units App 20070101033 - Chen; Wen-Tzer T. ; et al.	2007-05-03
Methods and apparatus for invalidating multiple address cache entries App 20070038797 - McBride; Chad B. ; et al.	2007-02-15
Conditional hardware scan dump data capture Grant 6,880,113 - Anderson , et al. April 12, 2	2005-04-12
Conditional hardware scan dump data capture App 20020166083 - Anderson, Gary D. ; et al.	2002-11-07
System and method for memory self-timed refresh for reduced power consumption Grant 6,334,167 - Gerchman , et al. December 25, 2	2001-12-25
Background completion of instruction and associated fetch request in a multithread processor Grant 6,088,788 - Borkenhagen , et al. July 11, 2	2000-07-11
Multiprocessor system having multiple classes of instructions for purposes of mutual interruptibility Grant 5,333,297 - Lemaire , et al. July 26, 1	1994-07-26
Apparatus for enabling byte or word addressing of storage organized on a word basis Grant 4,358,826 - Bodner , et al. November 9, 1	1982-11-09

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.