loadpatents
name:-0.014928817749023
name:-0.035593032836914
name:-0.0015280246734619
Worley; Eugene R. Patent Filings

Worley; Eugene R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Worley; Eugene R..The latest application filed is for "esd clamping transistor with switchable clamping modes of operation".

Company Profile
0.35.13
  • Worley; Eugene R. - Irvine CA US
  • Worley; Eugene R - Irvine CA
  • Worley; Eugene R. - San Diego CA
  • Worley; Eugene R. - Ivine CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Active diode having no gate and no shallow trench isolation
Grant 9,368,648 - Jalilizeinali , et al. June 14, 2
2016-06-14
ESD clamping transistor with switchable clamping modes of operation
Grant 9,054,520 - Worley , et al. June 9, 2
2015-06-09
Electrostatic discharge protection for class D power amplifiers
Grant 9,042,064 - Srivastava , et al. May 26, 2
2015-05-26
Esd Clamping Transistor With Switchable Clamping Modes Of Operation
App 20140204488 - Worley; Eugene R. ;   et al.
2014-07-24
Electrostatic Discharge Protection For Class D Power Amplifiers
App 20140098447 - Srivastava; Ankit ;   et al.
2014-04-10
Diode having a pocket implant blocked and circuits and methods employing same
Grant 8,665,570 - Jalilizeinali , et al. March 4, 2
2014-03-04
Charge pump electrostatic discharge protection
Grant 8,576,523 - Srivastava , et al. November 5, 2
2013-11-05
Circuit for measuring magnitude of electrostatic discharge (ESD) events for semiconductor chip bonding
Grant 8,536,893 - Worley , et al. September 17, 2
2013-09-17
Distributed building blocks of R-C clamping circuitry in semiconductor die core area
Grant 8,531,806 - Jalilizeinali , et al. September 10, 2
2013-09-10
Gated diode having at least one lightly-doped drain (LDD) implant blocked and circuits and methods employing same
Grant 8,531,805 - Worley September 10, 2
2013-09-10
Electrostatic discharge protection circuit
Grant 8,514,532 - Worley , et al. August 20, 2
2013-08-20
High voltage, high frequency ESD protection circuit for RF ICs
Grant 8,427,796 - Worley , et al. April 23, 2
2013-04-23
Charge Pump Electrostatic Discharge Protection
App 20120236444 - Srivastava; Ankit ;   et al.
2012-09-20
Distributed Building Blocks Of R-c Clamping Circuitry In Semiconductor Die Core Area
App 20120224284 - Jalilizeinali; Reza ;   et al.
2012-09-06
Amplifier with improved ESD protection circuitry
Grant 8,213,142 - Worley July 3, 2
2012-07-03
Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same
App 20120074496 - Jalilizeinali; Reza ;   et al.
2012-03-29
Optocoupler using silicon based LEDs
Grant 7,989,822 - Worley August 2, 2
2011-08-02
HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs
App 20110176245 - Worley; Eugene R. ;   et al.
2011-07-21
Active Diode Having No Gate and No Shallow Trench Isolation
App 20110084362 - Jalilizeinali; Reza ;   et al.
2011-04-14
Electrostatic Discharge Protection Circuit
App 20100321841 - Worley; Eugene R. ;   et al.
2010-12-23
Gated Diode Having At Least One Lightly-doped Drain (ldd) Implant Blocked And Circuits And Methods Employing Same
App 20100232077 - Worley; Eugene R.
2010-09-16
Circuit for Measuring Magnitude of Electrostatic Discharge (ESD) Events for Semiconductor Chip Bonding
App 20100225347 - Worley; Eugene R. ;   et al.
2010-09-09
ESD protection for integrated circuits having ultra thin gate oxides
Grant 7,746,606 - Worley June 29, 2
2010-06-29
Amplifier With Improved Esd Protection Circuitry
App 20100103572 - Worley; Eugene R.
2010-04-29
MOSFET having increased snap-back conduction uniformity
Grant 7,675,127 - Worley March 9, 2
2010-03-09
Electrostatic discharge clamp
Grant 6,927,957 - Bakulin , et al. August 9, 2
2005-08-09
Ballasting MOSFETs using staggered and segmented diffusion regions
Grant 6,927,458 - Worley August 9, 2
2005-08-09
ESD protection for integrated circuits having ultra thin gate oxides
App 20050152081 - Worley, Eugene R.
2005-07-14
Ballasting MOSFETs using staggered and segmented diffusion regions
App 20050029597 - Worley, Eugene R.
2005-02-10
Fully synthesisable and highly area efficient very large scale integration (VLSI) electrostatic discharge (ESD) protection circuit
Grant 6,643,109 - Li , et al. November 4, 2
2003-11-04
Integrated circuit device with embedded flash memory and method for manufacturing same
Grant 6,121,087 - Mann , et al. September 19, 2
2000-09-19
Electro-micro-mechanical shutters on transparent substrates
Grant 5,784,190 - Worley July 21, 1
1998-07-21
Method and apparatus for coupling multiple independent on-chip V.sub.dd busses to an ESD core clamp
Grant 5,654,862 - Worley , et al. August 5, 1
1997-08-05
Electro-micro-mechanical shutters on transparent substrates
Grant 5,552,925 - Worley September 3, 1
1996-09-03
Monolithic silicon opto-coupler using enhanced silicon based LEDS
Grant 5,466,948 - Worley November 14, 1
1995-11-14
ESD protection for submicron CMOS circuits
Grant 5,440,162 - Worley , et al. August 8, 1
1995-08-08
Optical isolation connections using integrated circuit techniques
Grant 5,438,210 - Worley August 1, 1
1995-08-01
Receiver designed with large output drive and having unique input protection circuit
Grant 5,124,578 - Worley , et al. June 23, 1
1992-06-23
CMOS TTL input buffer using a ratioed inverter with a threshold voltage adjusted N channel field effect transistor
Grant 5,017,811 - Worley May 21, 1
1991-05-21
Push-pull DCFL driver circuit
Grant 4,724,342 - Sato , et al. February 9, 1
1988-02-09

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed