Woods; Wayne H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Woods; Wayne H..The latest application filed is for "tunnel field-effect transistors with a gate-swing broken-gap heterostructure".

Company Profile

1.8.12

Woods; Wayne H. - Burlington VT
Woods; Wayne H. - Essex Junction VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Thermally-optimized metal fill for stacked chip systems Grant 9,058,460 - Daley , et al. June 16, 2	2015-06-16
Tunnel field-effect transistors with a gate-swing broken-gap heterostructure Grant 8,975,123 - Daley , et al. March 10, 2	2015-03-10
Tunnel Field-effect Transistors With A Gate-swing Broken-gap Heterostructure App 20150014633 - Daley; Douglas M. ; et al.	2015-01-15
Thermally-optimized Metal Fill For Stacked Chip Systems App 20140246757 - Daley; Douglas M. ; et al.	2014-09-04
On chip inductor with frequency dependent inductance Grant 8,823,136 - Ding , et al. September 2, 2	2014-09-02
On Chip Inductor With Frequency Dependent Inductance App 20130161785 - Ding; Hanyi ; et al.	2013-06-27
On-chip integrated voltage-controlled variable inductor, methods of making and tuning such variable inductors, and design structures integrating such variable inductors Grant 8,138,876 - Ding , et al. March 20, 2	2012-03-20
Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models Grant 8,141,013 - Woods , et al. March 20, 2	2012-03-20
Bias-controlled Deep Trench Substrate Noise Isolation Integrated Circuit Device Structures App 20110291238 - Chapman; Phillip Francis ; et al.	2011-12-01
Methods of fabricating coplanar waveguide structures Grant 8,028,406 - Ding , et al. October 4, 2	2011-10-04
Bias-controlled deep trench substrate noise isolation integrated circuit device structures Grant 8,021,941 - Chapman , et al. September 20, 2	2011-09-20
Bias-controlled Deep Trench Substrate Noise Isolation Integrated Circuit Device Structures App 20110018094 - Chapman; Phillip Francis ; et al.	2011-01-27
Method and System of Linking On-Chip Parasitic Coupling Capacitance Into Distributed Pre-Layout Passive Models App 20100333051 - Woods; Wayne H. ; et al.	2010-12-30
Coplanar waveguide integrated circuits having arrays of shield conductors connected by bridging conductors Grant 7,812,694 - Ding , et al. October 12, 2	2010-10-12
Methods Of Fabricating Coplanar Waveguide Structures App 20090249610 - Ding; Hanyi ; et al.	2009-10-08
Coplanar Waveguide Structures And Design Structures For Radiofrequency And Microwave Integrated Circuits App 20090251232 - Ding; Hanyi ; et al.	2009-10-08
On-chip Integrated Voltage-controlled Variable Inductor, Methods Of Making And Tuning Such Variable Inductors, And Design Structures Integrating Such Variable Inductors App 20090189725 - Ding; Hanyi ; et al.	2009-07-30
Method, Computer Program and System Providing for Semiconductor Processes Optimization App 20090031260 - Angyal; Matthew ; et al.	2009-01-29
Enabling Netlist For Modeling Of Technology Dependent Beol Process Variation App 20080066024 - Mina; Essam ; et al.	2008-03-13
Determining Geometrical Configuration Of Interconnect Structure App 20070298527 - Mina; Essam ; et al.	2007-12-27

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