Woo; Christy Mei-Chu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Woo; Christy Mei-Chu.The latest application filed is for "cu interconnects with composite barrier layers for wafer-to-wafer uniformity".

Company Profile

0.50.7

Woo; Christy Mei-Chu - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit contact system Grant 7,994,047 - Woo , et al. August 9, 2	2011-08-09
Composite barrier layers with controlled copper interface surface roughness Grant 7,755,194 - Marathe , et al. July 13, 2	2010-07-13
Composite tantalum nitride/tantalum copper capping layer Grant 7,157,795 - Erb , et al. January 2, 2	2007-01-02
Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration Grant 7,071,564 - Erb , et al. July 4, 2	2006-07-04
Method for determining metal work function by formation of Schottky diodes with shadow mask Grant 7,045,384 - Pan , et al. May 16, 2	2006-05-16
Method of forming composite barrier layers with controlled copper interface surface roughness Grant 7,033,940 - Marathe , et al. April 25, 2	2006-04-25
Conformal barrier liner in an integrated circuit interconnect Grant 6,989,604 - Woo , et al. January 24, 2	2006-01-24
Copper interconnects with metal capping layer and selective copper alloys Grant 6,979,625 - Woo , et al. December 27, 2	2005-12-27
Cu Interconnects With Composite Barrier Layers For Wafer-to-wafer Uniformity App 20050224979 - Marathe, Amit P. ; et al.	2005-10-13
Cu interconnects with composite barrier layers for wafer-to-wafer uniformity Grant 6,952,052 - Marathe , et al. October 4, 2	2005-10-04
Method for forming conductor reservoir volume for integrated circuit interconnects Grant 6,939,803 - Marathe , et al. September 6, 2	2005-09-06
One step deposition method for high-k dielectric and metal gate electrode Grant 6,893,910 - Woo , et al. May 17, 2	2005-05-17
Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode Grant 6,861,350 - Ngo , et al. March 1, 2	2005-03-01
Protection of low-k ILD during damascene processing with thin liner Grant 6,836,017 - Ngo , et al. December 28, 2	2004-12-28
Gate dielectric quality for replacement metal gate transistors Grant 6,830,998 - Pan , et al. December 14, 2	2004-12-14
Physical vapor deposition of nickel Grant 6,806,172 - Woo , et al. October 19, 2	2004-10-19
Protection of low-k ILD during damascene processing with thin liner App 20040147117 - Ngo, Minh Van ; et al.	2004-07-29
Titanium barrier for nickel silicidation of a gate electrode Grant 6,730,587 - Bertrand , et al. May 4, 2	2004-05-04
Copper interconnect with improved barrier layer Grant 6,727,592 - Woo , et al. April 27, 2	2004-04-27
Nickel silicide process using non-reactive spacer Grant 6,724,051 - Woo , et al. April 20, 2	2004-04-20
Protection low-k ILD during damascene processing with thin liner Grant 6,723,635 - Ngo , et al. April 20, 2	2004-04-20
Reactive pre-clean using reducing gas during nickel silicide process Grant 6,720,225 - Woo , et al. April 13, 2	2004-04-13
Nitrogen oxide plasma treatment for reduced nickel silicide bridging Grant 6,713,392 - Ngo , et al. March 30, 2	2004-03-30
Nitrogen-plasma treatment for reduced nickel silicide bridging Grant 6,661,067 - Ngo , et al. December 9, 2	2003-12-09
Conformal barrier liner in an integrated circuit interconnect Grant 6,657,304 - Woo , et al. December 2, 2	2003-12-02
Barrier layer integrity test Grant 6,633,083 - Woo , et al. October 14, 2	2003-10-14
Method Of Determining Barrier Layer Effectiveness For Preventing Metallization Diffusion By Forming A Test Specimen Device And Using A Metal Penetration Measurement Technique For Fabricating A Production Semiconductor Device And A Test Specimen Device Thereby Formed Grant 6,617,176 - Sanchez, Jr. , et al. September 9, 2	2003-09-09
Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Grant 6,605,513 - Paton , et al. August 12, 2	2003-08-12
Testing dielectric and barrier layers for integrated circuit interconnects Grant 6,599,835 - Marathe , et al. July 29, 2	2003-07-29
Selective deposition in integrated circuit interconnects Grant 6,590,288 - Woo , et al. July 8, 2	2003-07-08
Process for forming fully silicided gates Grant 6,562,718 - Xiang , et al. May 13, 2	2003-05-13
Method of forming low resistance barrier on low k interconnect Grant 6,555,461 - Woo , et al. April 29, 2	2003-04-29
Fully nickel silicided metal gate with shallow junction formed Grant 6,555,453 - Xiang , et al. April 29, 2	2003-04-29
Cobalt barrier for nickel silicidation of a gate electrode Grant 6,541,866 - Bertrand , et al. April 1, 2	2003-04-01
Graded low-k middle-etch stop layer for dual-inlaid patterning Grant 6,525,428 - Ngo , et al. February 25, 2	2003-02-25
Copper interconnects with improved electromigration resistance and low resistivity Grant 6,525,425 - Woo , et al. February 25, 2	2003-02-25
HDP treatment for reduced nickel silicide bridging Grant 6,521,529 - Ngo , et al. February 18, 2	2003-02-18
Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer Grant 6,509,267 - Woo , et al. January 21, 2	2003-01-21
Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability Grant 6,506,668 - Woo , et al. January 14, 2	2003-01-14
Method for forming conductor reservoir volume for integrated circuit interconnects App 20020195714 - Marathe, Amit P. ; et al.	2002-12-26
Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface Grant 6,495,460 - Bertrand , et al. December 17, 2	2002-12-17
Nitrogen oxide plasma treatment for reduced nickel silicide bridging Grant 6,483,154 - Ngo , et al. November 19, 2	2002-11-19
Barrier layer integrity test App 20020151093 - Woo, Christy Mei-Chu ; et al.	2002-10-17
Double silicide formation in polysicon gate without silicide in source/drain extensions Grant 6,451,693 - Woo , et al. September 17, 2	2002-09-17
Method for improving seed layer electroplating for semiconductor Grant 6,440,289 - Woo , et al. August 27, 2	2002-08-27
Plating system with secondary ring anode for a semiconductor wafer Grant 6,425,991 - Tran , et al. July 30, 2	2002-07-30
Conductor reservoir volume for integrated circuit interconnects App 20020093057 - Marathe, Amit P. ; et al.	2002-07-18
Method Of Forming Nickel Silicide Using A One-step Rapid Thermal Anneal Process And Backend Processing App 20020068408 - Paton, Eric N. ; et al.	2002-06-06
Dual layer silicide formation using an aluminum barrier to reduce surface roughness at silicide/junction interface App 20020068444 - Bertrand, Jacques ; et al.	2002-06-06
Nickel silicide stripping after nickel silicide formation Grant 6,362,095 - Woo , et al. March 26, 2	2002-03-26
Method of manufacturing a semiconductor device having copper interconnects Grant 6,346,479 - Woo , et al. February 12, 2	2002-02-12
Consistent plating system for electroplating Grant 6,270,635 - Woo August 7, 2	2001-08-07
Slurry for chemical mechanical polishing of copper Grant 6,143,656 - Yang , et al. November 7, 2	2000-11-07
Method of forming a void free copper interconnects Grant 6,121,141 - Woo , et al. September 19, 2	2000-09-19
Method for implanting semiconductor conductive layers Grant 6,117,770 - Pramanick , et al. September 12, 2	2000-09-12
Electroplating uniformity by diffuser design Grant 6,103,085 - Woo , et al. August 15, 2	2000-08-15
Copper/low dielectric interconnect formation with reduced electromigration Grant 6,096,648 - Lopatin , et al. August 1, 2	2000-08-01

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