loadpatents
name:-0.012645959854126
name:-0.0038270950317383
name:-0.00094008445739746
WONTOR; DAVID G. Patent Filings

WONTOR; DAVID G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for WONTOR; DAVID G..The latest application filed is for "bga package with traces for plating pads under the chip".

Company Profile
0.7.8
  • WONTOR; DAVID G. - DUBLIN CA
  • Wontor; David G. - Austin TX
  • Wontor; David G. - Allen TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Bga Package With Traces For Plating Pads Under The Chip
App 20120013003 - RHYNER; KENNETH R. ;   et al.
2012-01-19
Circuit device with at least partial packaging and method for forming
Grant 8,072,062 - Leal , et al. December 6, 2
2011-12-06
BGA package with traces for plating pads under the chip
Grant 8,053,349 - Rhyner , et al. November 8, 2
2011-11-08
Mechanical integrity evaluation of low-k devices with bump shear
Grant 7,622,309 - Su , et al. November 24, 2
2009-11-24
BGA Package with Traces for Plating Pads Under the Chip
App 20090115072 - RHYNER; KENNETH R. ;   et al.
2009-05-07
Circuit Device With At Least Partial Packaging And Method For Forming
App 20080142960 - Leal; George R. ;   et al.
2008-06-19
Circuit device with at least partial packaging and method for forming
Grant 7,361,987 - Leal , et al. April 22, 2
2008-04-22
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor
Grant 7,247,552 - Pozder , et al. July 24, 2
2007-07-24
Mechanical integrity evaluation of low-k devices with bump shear
App 20060292711 - Su; Peng ;   et al.
2006-12-28
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor
App 20060154470 - Pozder; Scott K. ;   et al.
2006-07-13
Circuit device with at least partial packaging and method for forming
App 20060012036 - Leal; George R. ;   et al.
2006-01-19
Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
Grant 6,921,975 - Leal , et al. July 26, 2
2005-07-26
Circuit device with at least partial packaging and method for forming
Grant 6,838,776 - Leal , et al. January 4, 2
2005-01-04
Circuit device with at least partial packaging and method for forming
App 20040207077 - Leal, George R. ;   et al.
2004-10-21
Circuit device with at least partial packaging and method for forming
App 20040207068 - Leal, George R. ;   et al.
2004-10-21

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed