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name:-0.013771057128906
name:-0.013134002685547
name:-0.00042486190795898
Wong; Tak Kwong Patent Filings

Wong; Tak Kwong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wong; Tak Kwong.The latest application filed is for "systems and methods for power management in electronic devices".

Company Profile
0.11.10
  • Wong; Tak Kwong - Milpitas CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Overvoltage protection circuits and methods of operating same
Grant 9,793,708 - Glaser , et al. October 17, 2
2017-10-17
Systems and methods for power management in electronic devices
Grant 8,892,930 - Yeh , et al. November 18, 2
2014-11-18
Systems and methods for monitoring and controlling binary state devices using a memory device
Grant 7,904,667 - Wang , et al. March 8, 2
2011-03-08
Input termination for delay locked loop feedback with impedance matching
Grant 7,898,288 - Wong March 1, 2
2011-03-01
Systems and methods for monitoring and controlling binary state devices using a memory device
Grant 7,747,828 - Wang , et al. June 29, 2
2010-06-29
Impedance matching logic
Grant 7,688,105 - Wong March 30, 2
2010-03-30
Systems And Methods For Power Management In Electronic Devices
App 20100031073 - Yeh; Tzong-Kwang Henry ;   et al.
2010-02-04
Impedance Matching Logic
App 20100007373 - Wong; Tak Kwong
2010-01-14
Using a delay clock to optimize the timing margin of sequential logic
Grant 7,647,535 - Wong January 12, 2
2010-01-12
Modular distributive arithmetic logic unit
Grant 7,571,300 - Wong August 4, 2
2009-08-04
Modular Distributive Arithmetic Logic Unit
App 20080168256 - Wong; Tak Kwong
2008-07-10
Using A Delay Clock To Optimize The Timing Margin Of Sequential Logic
App 20080143383 - Wong; Tak Kwong
2008-06-19
Input Termination For Delay Locked Loop Feedback With Impedance Matching
App 20080136443 - Wong; Tak Kwong
2008-06-12
Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
Grant 7,162,673 - Wong January 9, 2
2007-01-09
Systems and methods for monitoring and controlling binary state devices using a memory device
App 20060277372 - Wang; Yunsheng ;   et al.
2006-12-07
Systems and methods for monitoring and controlling binary state devices using a memory device
App 20060106989 - Wang; Yunsheng ;   et al.
2006-05-18
Statistics engine
App 20060101152 - Yeh; Tzong-Kwang ;   et al.
2006-05-11
Bitline layout in a dual port memory array
App 20060092749 - Wong; Tak Kwong
2006-05-04
Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
App 20050108604 - Wong, Tak Kwong
2005-05-19
ESD damage protection using a clamp circuit
Grant 6,069,782 - Lien , et al. May 30, 2
2000-05-30

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