Wong; Myron W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wong; Myron W..The latest application filed is for "input buffer with hysteresis option".

Company Profile

0.14.0

Wong; Myron W. - Fremont CA
Wong; Myron W. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Input buffer with hysteresis option Grant 6,965,251 - Tran , et al. November 15, 2	2005-11-15
Apparatus and method for margin testing single polysilicon EEPROM cells Grant 6,781,883 - Madurawe , et al. August 24, 2	2004-08-24
Cross coupled N-channel negative pump Grant 6,664,846 - Maung , et al. December 16, 2	2003-12-16
Apparatus and method for margin testing single polysilicon EEPROM cells Grant 6,646,919 - Madurawe , et al. November 11, 2	2003-11-11
Output buffer predriver with edge compensation Grant 6,236,237 - Wong , et al. May 22, 2	2001-05-22
Method and circuit for reducing output ground and power bounce noise Grant 6,184,703 - Vest , et al. February 6, 2	2001-02-06
Voltage ramp rate control circuit Grant 5,945,870 - Chu , et al. August 31, 1	1999-08-31
Biasing scheme for reducing stress and improving reliability in EEPROM cells Grant 5,905,675 - Madurawe , et al. May 18, 1	1999-05-18
Sense amplifier with individually optimized high and low power modes Grant 5,850,365 - Reese , et al. December 15, 1	1998-12-15
Sense amplifier with feedback and stabilization Grant 5,525,917 - Wong , et al. June 11, 1	1996-06-11
Method and apparatus for enhanced EPROM and EEPROM programmability and process scaling Grant 5,493,526 - Turner , et al. February 20, 1	1996-02-20
Advanced signal driving buffer with directional input transition detection Grant 5,414,312 - Wong May 9, 1	1995-05-09
Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements Grant 5,371,422 - Patel , et al. December 6, 1	1994-12-06
Programmable logic device with redundant circuitry Grant 5,369,314 - Patel , et al. November 29, 1	1994-11-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.