loadpatents
name:-0.0046761035919189
name:-1.0314490795135
name:-0.014846801757812
Wong; Hiu Yung Patent Filings

Wong; Hiu Yung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wong; Hiu Yung.The latest application filed is for "heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions".

Company Profile
7.11.4
  • Wong; Hiu Yung - Mountain View CA
  • Wong; Hiu Yung - Cupertino CA
  • Wong; Hiu-Yung - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Machine learning method and framework for optimizing setups for accurate, speedy and robust TCAD simulations
Grant 11,348,017 - Wong , et al. May 31, 2
2022-05-31
Using threading dislocations in GaN/Si systems to generate physically unclonable functions
Grant 11,152,313 - Wong , et al. October 19, 2
2021-10-19
Constricted junctionless FinFET/nanowire/nanosheet device having cascode portion
Grant 10,777,638 - Wong , et al. Sept
2020-09-15
Local band-to-band-tunneling model for TCAD simulation
Grant 10,769,339 - Wong , et al. Sep
2020-09-08
Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties
Grant 10,733,348 - Wong , et al.
2020-08-04
On-chip heating and self-annealing in FinFETs with anti-punch-through implants
Grant 10,699,914 - Wong , et al.
2020-06-30
Normally-off gallium oxide field-effect transistor
Grant 10,644,107 - Wong , et al.
2020-05-05
Heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions
Grant 10,403,625 - Wong , et al. Sep
2019-09-03
Heterojunction Field Effect Transistor Device with Serially Connected Enhancement Mode and Depletion Mode Gate Regions
App 20190148371 - Wong; Hiu Yung ;   et al.
2019-05-16
Heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions
Grant 10,128,232 - Wong , et al. November 13, 2
2018-11-13
Tined Gate To Control Threshold Voltage In A Device Formed Of Materials Having Piezoelectric Properties
App 20180300443 - Wong; Hiu Yung ;   et al.
2018-10-18
Heterojunction Field Effect Transistor Device with Serially Connected Enhancement Mode and Depletion Mode Gate Regions
App 20170338224 - Wong; Hiu Yung ;   et al.
2017-11-23
Forming metal-semiconductor films having different thicknesses within different regions of an electronic device
Grant 7,880,221 - Kim , et al. February 1, 2
2011-02-01
Forming Metal-semiconductor Films Having Different Thicknesses Within Different Regions Of An Electronic Device
App 20090140325 - Kim; Eunha ;   et al.
2009-06-04
Forming metal-semiconductor films having different thicknesses within different regions of an electronic device
Grant 7,482,217 - Kim , et al. January 27, 2
2009-01-27

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