Wohl; Peter

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wohl; Peter.The latest application filed is for "increasing compression by reducing padding patterns".

Company Profile

2.27.16

Wohl; Peter - Williston VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Per-shift X-tolerant logic built-in self-test Grant 11,422,186 - Waicukauski , et al. August 23, 2	2022-08-23
Reducing X-masking effect for linear time compactors Grant 10,908,213 - Gizdarski , et al. February 2, 2	2021-02-02
Increasing compression by reducing padding patterns Grant 10,346,557 - Wohl , et al. July 9, 2	2019-07-09
Increasing Compression by Reducing Padding Patterns App 20180156869 - Wohl; Peter ; et al.	2018-06-07
Diagnosis and debug with truncated simulation Grant 9,404,972 - Wohl , et al. August 2, 2	2016-08-02
Diagnosis And Debug With Truncated Simulation App 20160025810 - Wohl; Peter ; et al.	2016-01-28
Diagnosis and debug using truncated simulation Grant 9,171,123 - Wohl , et al. October 27, 2	2015-10-27
Two-level compression through selective reseeding Grant 9,157,961 - Wohl , et al. October 13, 2	2015-10-13
Increasing PRPG-based compression by delayed justification Grant 9,152,752 - Wohl , et al. October 6, 2	2015-10-06
Diagnosis And Debug Using Truncated Simulation App 20150067629 - Wohl; Peter ; et al.	2015-03-05
Two-Level Compression Through Selective Reseeding App 20140281774 - Wohl; Peter ; et al.	2014-09-18
Fully X-tolerant, very high scan compression scan test systems and techniques Grant 8,645,780 - Wohl , et al. February 4, 2	2014-02-04
Fully X-Tolerant, Very High Scan Compression Scan Test Systems And Techniques App 20130268817 - Wohl; Peter ; et al.	2013-10-10
ATPG and compression by using majority gates Grant 8,549,372 - Wohl , et al. October 1, 2	2013-10-01
Increasing PRPG-Based Compression By Delayed Justification App 20130232458 - Wohl; Peter ; et al.	2013-09-05
Atpg And Compression By Using Majority Gates App 20130232459 - Wohl; Peter ; et al.	2013-09-05
Fully X-tolerant, very high scan compression scan test systems and techniques Grant 8,464,115 - Wohl , et al. June 11, 2	2013-06-11
Increasing PRPG-based compression by delayed justification Grant 8,429,473 - Wohl , et al. April 23, 2	2013-04-23
Fully X-tolerant, Very High Scan Compression Scan Test Systems And Techniques App 20110258503 - Wohl; Peter ; et al.	2011-10-20
Increasing PRPG-Based Compression by Delayed Justification App 20110231805 - Wohl; Peter ; et al.	2011-09-22
Fully X-tolerant, very high scan compression scan test systems and techniques Grant 7,979,763 - Wohl , et al. July 12, 2	2011-07-12
Increasing scan compression by using X-chains Grant 7,958,472 - Wohl , et al. June 7, 2	2011-06-07
Launch-on-shift support for on-chip-clocking Grant 7,882,410 - Ayres , et al. February 1, 2	2011-02-01
Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit Grant 7,823,034 - Wohl , et al. October 26, 2	2010-10-26
Scan compression circuit and method of design therefor Grant 7,814,444 - Wohl , et al. October 12, 2	2010-10-12
Fully X-Tolerant, Very High Scan Compression Scan Test Systems And Techniques App 20100100781 - Wohl; Peter ; et al.	2010-04-22
Increasing Scan Compression By Using X-Chains App 20100083199 - Wohl; Peter ; et al.	2010-04-01
Launch-On-Shift Support for On-Chip-Clocking App 20080320348 - Ayres; Timothy N. ; et al.	2008-12-25
Scan compression circuit and method of design therefor App 20080256497 - Wohl; Peter ; et al.	2008-10-16
Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit App 20080256274 - Wohl; Peter ; et al.	2008-10-16
Deterministic BIST architecture tolerant of uncertain scan chain outputs Grant 7,237,162 - Wohl , et al. June 26, 2	2007-06-26
Deterministic bist architecture including MISR filter Grant 6,993,694 - Kapur , et al. January 31, 2	2006-01-31
Method and system for generating an ATPG model of a memory from behavioral descriptions Grant 6,959,272 - Wohl , et al. October 25, 2	2005-10-25
Efficient compression and application of deterministic patterns in a logic BIST architecture Grant 6,950,974 - Wohl , et al. September 27, 2	2005-09-27
System and method for time slicing deterministic patterns for reseeding in logic built-in self-test Grant 6,807,646 - Williams , et al. October 19, 2	2004-10-19
Method And System For Generating An Atpg Model Of A Memory From Behavioral Descriptions App 20040167764 - Wohl, Peter ; et al.	2004-08-26
Method and system for controlling test data volume in deterministic test pattern generation Grant 6,385,750 - Kapur , et al. May 7, 2	2002-05-07
System and process of extracting gate-level descriptions from simulation tables for formal verification Grant 6,247,165 - Wohl , et al. June 12, 2	2001-06-12
Integrated circuit clocking technique and circuit therefor Grant 5,668,492 - Pedersen , et al. September 16, 1	1997-09-16

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