Woerner; Alexander

Patent Applications and Registrations

Patent applications and USPTO patent grants for Woerner; Alexander.The latest application filed is for "defective memory column replacement with load isolation".

Company Profile

0.11.12

Woerner; Alexander - Boebingen DE
Woerner; Alexander - Boeblingen DE
Woerner; Alexander - Bochingen DE
Woerner; Alexander - Bocbingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system to fix early mode slacks in a circuit design Grant 9,058,456 - Haller , et al. June 16, 2	2015-06-16
Defective memory column replacement with load isolation Grant 8,964,493 - Penth , et al. February 24, 2	2015-02-24
Defective Memory Column Replacement With Load Isolation App 20140192602 - Penth; Silke ; et al.	2014-07-10
Method And System To Fix Early Mode Slacks In A Circuit Design App 20140089880 - Haller; Wilhelm ; et al.	2014-03-27
Method and system for generating a placement layout of a VLSI circuit design Grant 8,631,376 - Werner , et al. January 14, 2	2014-01-14
Simd Accelerator For Data Comparison App 20130227250 - Haller; Wilhelm ; et al.	2013-08-29
Generation of an end point report for a timing simulation of an integrated circuit Grant 8,522,182 - Krauch , et al. August 27, 2	2013-08-27
Multistage, hybrid synthesis processing facilitating integrated circuit layout Grant 8,316,335 - Barowski , et al. November 20, 2	2012-11-20
Generation Of An End Point Report For A Timing Simulation Of An Integrated Circuit App 20120246606 - KRAUCH; Ulrich ; et al.	2012-09-27
Method and System for Generating a Placement Layout of a VLSI Circuit Design App 20120174051 - Werner; Tobias T. ; et al.	2012-07-05
Multistage, Hybrid Synthesis Processing Facilitating Integrated Circuit Layout App 20120151429 - BAROWSKI; Harry ; et al.	2012-06-14
System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow Width App 20120005643 - Schroeder; Friedrich ; et al.	2012-01-05
Topology for a n-way XOR/XNOR circuit Grant 7,557,614 - Bonsels , et al. July 7, 2	2009-07-07
Method for comparing two designs of electronic circuits Grant 7,546,565 - Fenkes , et al. June 9, 2	2009-06-09
Method for creating a layout for an electronic circuit Grant 7,490,310 - Koehl , et al. February 10, 2	2009-02-10
Layout Generator for Routing and Designing an LSI App 20080301616 - Krauch; Ulrich ; et al.	2008-12-04
Method for comparing two designs of electronic circuits App 20080172640 - Fenkes; Joachim ; et al.	2008-07-17
Automatic method for routing and designing an LSI Grant 7,401,312 - Krauch , et al. July 15, 2	2008-07-15
Method and Tool for Creating a Layout for an Electronic Circuit App 20070089079 - Koehl; Juergen ; et al.	2007-04-19
Automatic method for routing and designing an LSI App 20050132319 - Krauch, Ulrich ; et al.	2005-06-16

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