WITTIG; Ralph D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for WITTIG; Ralph D..The latest application filed is for "control and reconfiguration of data flow graphs on heterogeneous computing platform".

Company Profile

7.46.16

WITTIG; Ralph D. - Menlo Park CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Control And Reconfiguration Of Data Flow Graphs On Heterogeneous Computing Platform App 20220206766 - HSU; Chia-Jui ; et al.	2022-06-30
Control and reconfiguration of data flow graphs on heterogeneous computing platform Grant 11,281,440 - Hsu , et al. March 22, 2	2022-03-22
Dataflow Graph Programming Environment For A Heterogenous Processing System App 20220058005 - GUPTA; Shail Aditya ; et al.	2022-02-24
Dataflow graph programming environment for a heterogenous processing system Grant 11,204,745 - Gupta , et al. December 21, 2	2021-12-21
Streaming interconnect architecture for data processing engine array Grant 10,990,552 - Bilski , et al. April 27, 2	2021-04-27
Data processing engine arrangement in a device Grant 10,866,753 - Noguera Serra , et al. December 15, 2	2020-12-15
Compilation flow for a heterogeneous multi-core architecture Grant 10,860,766 - Sivaraman , et al. December 8, 2	2020-12-08
Dataflow Graph Programming Environment For A Heterogenous Processing System App 20200371761 - Gupta; Shail Aditya ; et al.	2020-11-26
Compilation Flow For A Heterogeneous Multi-core Architecture App 20200372200 - Sivaraman; Mukund ; et al.	2020-11-26
Dynamically structured single instruction, multiple data (SIMD) instructions Grant 10,824,434 - Settle , et al. November 3, 2	2020-11-03
Control and reconfiguration of data flow graphs on heterogeneous computing platform Grant 10,802,807 - Hsu , et al. October 13, 2	2020-10-13
Device with data processing engine array Grant 10,747,690 - Bilski , et al. A	2020-08-18
Device With Data Processing Engine Array App 20190303311 - Bilski; Goran HK ; et al.	2019-10-03
Data Processing Engine Arrangement In A Device App 20190303033 - Noguera Serra; Juan J. ; et al.	2019-10-03
Heterogeneous multiprocessor platform targeting programmable integrated circuits Grant 9,846,660 - Styles , et al. December 19, 2	2017-12-19
Heterogeneous Multiprocessor Platform Targeting Programmable Integrated Circuits App 20160132441 - Styles; Henry E. ; et al.	2016-05-12
Heterogeneous multiprocessor program compilation targeting programmable integrated circuits Grant 9,218,443 - Styles , et al. December 22, 2	2015-12-22
Transaction-level lockstep Grant 8,479,042 - James-Roxby , et al. July 2, 2	2013-07-02
Coprocessor interface architecture and methods of operating the same Grant 8,447,957 - Carrillo , et al. May 21, 2	2013-05-21
Methods and systems with transaction-level lockstep Grant 8,443,230 - James-Roxby , et al. May 14, 2	2013-05-14
Segmentation and reassembly of a data value communicated via interrupt transactions Grant 8,352,659 - Styles , et al. January 8, 2	2013-01-08
Providing multiple selectable configuration sources for programmable integrated circuits with fail safe mechanism Grant 8,296,557 - Ballantyne , et al. October 23, 2	2012-10-23
System and method for open drain/open collector structures in an integrated circuit Grant 7,948,269 - Ballantyne , et al. May 24, 2	2011-05-24
Generic buffer circuits and methods for out of band signaling Grant 7,786,762 - Ballantyne , et al. August 31, 2	2010-08-31
Generic Buffer Circuits And Methods For Out Of Band Signaling App 20100183081 - Ballantyne; Richard S. ; et al.	2010-07-22
Event-driven simulation of IP using third party event-driven simulators Grant 7,721,090 - Deepak , et al. May 18, 2	2010-05-18
Method and system for fast linked processor in a system on a chip (SoC) Grant 7,340,585 - Ganesan , et al. March 4, 2	2008-03-04
Method and system for designing a multiprocessor Grant 7,310,594 - Ganesan , et al. December 18, 2	2007-12-18
Configurable logic element with expander structures Grant 7,248,073 - New , et al. July 24, 2	2007-07-24
Method and apparatus for providing self-implementing hardware-software libraries Grant 7,243,330 - Ganesan , et al. July 10, 2	2007-07-10
Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks Grant 7,181,718 - Bilski , et al. February 20, 2	2007-02-20
Configurable logic element with expander structures App 20070035328 - New; Bernard J. ; et al.	2007-02-15
Configurable logic element with expander structures Grant 7,145,360 - New , et al. December 5, 2	2006-12-05
Softpal implementation and mapping technology for FPGAs with dedicated resources Grant 7,111,273 - Ganesan , et al. September 19, 2	2006-09-19
Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks Grant 6,946,874 - Bilski , et al. September 20, 2	2005-09-20
Configurable logic element with expander structures App 20050062498 - New, Bernard J. ; et al.	2005-03-24
Configurable logic element with expander structures Grant 6,847,229 - New , et al. January 25, 2	2005-01-25
Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks Grant 6,803,786 - Bilski , et al. October 12, 2	2004-10-12
Configurable logic element with expander structures App 20040032283 - New, Bernard J. ; et al.	2004-02-19
Configurable logic element with expander structures Grant 6,630,841 - New , et al. October 7, 2	2003-10-07
Configurable logic block for PLD with logic gate for combining output with another configurable logic block Grant 6,603,332 - Kaviani , et al. August 5, 2	2003-08-05
Method for implementing large multiplexers with FPGA lookup tables Grant 6,505,337 - Wittig , et al. January 7, 2	2003-01-07
Logic/memory circuit having a plurality of operating modes Grant 6,501,296 - Wittig , et al. December 31, 2	2002-12-31
Hetergeneous method for determining module placement in FPGAs Grant 6,457,164 - Hwang , et al. September 24, 2	2002-09-24
Configurable logic element with expander structures App 20020125910 - New, Bernard J. ; et al.	2002-09-12
Configurable logic block for PLD with logic gate for combining output with another configurable logic block App 20020079921 - Kaviani, Alireza S. ; et al.	2002-06-27
Configurable lookup table for programmable logic devices Grant 6,400,180 - Wittig , et al. June 4, 2	2002-06-04
Configurable logic element with expander structures Grant 6,396,302 - New , et al. May 28, 2	2002-05-28
Configurable logic element with expander structures App 20010045844 - New, Bernard J. ; et al.	2001-11-29
Logic/memory circuit having a plurality of operating modes App 20010043082 - Wittig, Ralph D. ; et al.	2001-11-22
Context-sensitive self implementing modules Grant 6,292,925 - Dellinger , et al. September 18, 2	2001-09-18
Method for specifying routing in a logic module by direct module communication Grant 6,260,182 - Mohan , et al. July 10, 2	2001-07-10
Heterogeneous method for determining module placement in FPGAs Grant 6,243,851 - Hwang , et al. June 5, 2	2001-06-05
Methods and media for utilizing symbolic expressions in circuit modules App 20010001881 - Mohan, Sundararajarao ; et al.	2001-05-24
Method for constraining circuit element positions in structured layouts Grant 6,237,129 - Patterson , et al. May 22, 2	2001-05-22
FPGA modules parameterized by expressions Grant 6,216,258 - Mohan , et al. April 10, 2	2001-04-10
Method for implementing large multiplexers with FPGA lookup tables Grant 6,191,610 - Wittig , et al. February 20, 2	2001-02-20
FPGA configurable logic block with multi-purpose logic/memory circuit Grant 6,150,838 - Wittig , et al. November 21, 2	2000-11-21
Method for implementing large multiplexers with FPGA lookup tables Grant 6,118,300 - Wittig , et al. September 12, 2	2000-09-12

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