Wisor; Michael T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wisor; Michael T..The latest application filed is for "hardware initialization method that is independent of boot code architecture".

Company Profile

0.21.0

Wisor; Michael T. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hardware initialization method that is independent of boot code architecture Grant 7,219,219 - Wisor May 15, 2	2007-05-15
Non-volatile memory system having a programmably selectable boot code section size Grant 7,206,914 - Wisor April 17, 2	2007-04-17
Non-volatile memory system having a programmably selectable boot code section size Grant 6,823,435 - Wisor November 23, 2	2004-11-23
Hardware-based system for enabling data transfers between a CPU and chip set logic of a computer system on both edges of bus clock signal Grant 6,076,160 - Wisor June 13, 2	2000-06-13
Bios memory and multimedia data storage combination Grant 5,999,476 - Dutton , et al. December 7, 1	1999-12-07
System and method for providing microprocessor serialization using programmable fuses Grant 5,946,497 - Lee , et al. August 31, 1	1999-08-31
Method and apparatus for serializing microprocessor identification numbers Grant 5,933,620 - Lee , et al. August 3, 1	1999-08-03
System and method for simulating a multiprocessor environment for testing a multiprocessing interrupt controller Grant 5,862,366 - Schmidt , et al. January 19, 1	1999-01-19
System and method for reconfiguring configuration registers of a PCI bus device in response to a change in clock signal frequency Grant 5,815,734 - Lee , et al. September 29, 1	1998-09-29
System for receiving peripheral device capability information and selectively disabling corresponding processing unit function when the device failing to support such function Grant 5,799,203 - Lee , et al. August 25, 1	1998-08-25
System and method for testing and debugging a multiprocessing interrupt controller Grant 5,790,871 - Qureshi , et al. August 4, 1	1998-08-04
Method and apparatus for software access to a microprocessor serial number Grant 5,790,663 - Lee , et al. August 4, 1	1998-08-04
Method and apparatus for dynamically displaying and causing the execution of software diagnostic/test programs for the silicon validation of microprocessors Grant 5,768,499 - Treadway , et al. June 16, 1	1998-06-16
Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency Grant 5,678,065 - Lee , et al. October 14, 1	1997-10-14
Immediate system management interrupt source with associated reason register Grant 5,671,424 - Wisor , et al. September 23, 1	1997-09-23
Fail-safe communication abort mechanism for parallel ports with selectable NMI or parallel port interrupt Grant 5,666,559 - Wisor , et al. September 9, 1	1997-09-09
Power management control technique for timer tick activity within an interrupt driven computer system Grant 5,664,205 - O'Brien , et al. September 2, 1	1997-09-02
System and method for enabling and disabling a clock run function to control a peripheral bus clock signal Grant 5,625,807 - Lee , et al. April 29, 1	1997-04-29
Power management system distinguishing between primary and secondary system activity Grant 5,511,203 - Wisor , et al. April 23, 1	1996-04-23
Power management unit including software configurable state register and time-out counters for protecting against misbehaved software Grant 5,504,910 - Wisor , et al. April 2, 1	1996-04-02
Disable technique employed during low battery conditions within a portable computer system Grant 5,442,794 - Wisor , et al. August 15, 1	1995-08-15

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