Wise; Richard Stephen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wise; Richard Stephen.The latest application filed is for "method of controlling a patterning process, lithographic apparatus, metrology apparatus lithographic cell and associated compute".

Company Profile

2.18.16

Wise; Richard Stephen - Los Gatos CA
Wise; Richard Stephen - Ridgefield CT
Wise; Richard Stephen - Los Altos CA
Wise; Richard Stephen - Newburgh NY US
Wise; Richard Stephen - New Windsor NY
Wise; Richard Stephen - Beacon NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of controlling a patterning process, lithographic apparatus, metrology apparatus lithographic cell and associated computer program Grant 11,048,174 - Kubis , et al. June 29, 2	2021-06-29
Method Of Controlling A Patterning Process, Lithographic Apparatus, Metrology Apparatus Lithographic Cell And Associated Compute App 20200233311 - KUBIS; Michael ; et al.	2020-07-23
Advanced interconnect with air gap Grant 10,546,743 - Zhang , et al. Ja	2020-01-28
Advanced Interconnect With Air Gap App 20180144926 - Zhang; John H. ; et al.	2018-05-24
Trench structure for high performance interconnection lines of different resistivity and method of making same Grant 9,786,551 - Zhang , et al. October 10, 2	2017-10-10
Interconnect structure having large self-aligned vias Grant 9,659,820 - Zhang , et al. May 23, 2	2017-05-23
Interconnect structure having large self-aligned vias Grant 9,658,523 - Zhang , et al. May 23, 2	2017-05-23
Interconnect Structure Having Large Self-aligned Vias App 20160247722 - Zhang; John H. ; et al.	2016-08-25
Interconnect structure having large self-aligned vias Grant 9,391,020 - Zhang , et al. July 12, 2	2016-07-12
Trench interconnect having reduced fringe capacitance Grant 9,214,429 - Zhang , et al. December 15, 2	2015-12-15
Trench Structure For High Performance Interconnection Lines Of Different Resistivity And Method Of Making Same App 20150311113 - Zhang; John Hongguang ; et al.	2015-10-29
Interconnect Structure Having Large Self-aligned Vias App 20150279780 - Zhang; John H. ; et al.	2015-10-01
Interconnect Structure Having Large Self-aligned Vias App 20150279784 - Zhang; John H. ; et al.	2015-10-01
Advanced Interconnect With Air Gap App 20150162277 - Zhang; John H. ; et al.	2015-06-11
Trench Interconnect Having Reduced Fringe Capacitance App 20150162278 - Zhang; John H. ; et al.	2015-06-11
Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers Grant 8,829,612 - Cheng , et al. September 9, 2	2014-09-09
On-chip cooling for integrated circuits Grant 8,492,295 - Kumar , et al. July 23, 2	2013-07-23
On-chip Cooling For Integrated Circuits App 20130012018 - Kumar; Kaushik A. ; et al.	2013-01-10
On-chip cooling systems for integrated circuits Grant 8,298,966 - Kumar , et al. October 30, 2	2012-10-30
CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs Grant 8,018,005 - Doris , et al. September 13, 2	2011-09-13
Method Of Forming Asymmetric Spacers And Methods Of Fabricating Semiconductor Device Using Asymmetric Spacers App 20110108895 - Cheng; Kangguo ; et al.	2011-05-12
Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers Grant 7,892,928 - Cheng , et al. February 22, 2	2011-02-22
Cmos (complementary Metal Oxide Semiconductor) Devices Having Metal Gate Nfets And Poly-silicon Gate Pfets App 20100258875 - Doris; Bruce Bennett ; et al.	2010-10-14
CMOS (complementary metal oxide semiconductor) devices having metal gate NFETS and poly-silicon gate PFETS Grant 7,749,830 - Doris , et al. July 6, 2	2010-07-06
On-chip Cooling Systems For Integrated Circuits App 20100136800 - Kumar; Kaushik A. ; et al.	2010-06-03
On-chip cooling systems for integrated circuits Grant 7,659,616 - Kumar , et al. February 9, 2	2010-02-09
Cmos (complementary Metal Oxide Semiconductor) Devices Having Metal Gate Nfets And Poly-silicon Gate Pfets App 20090194820 - Doris; Bruce Bennett ; et al.	2009-08-06
On-chip Cooling Systems For Integrated Circuits App 20090096056 - Kumar; Kaushik A. ; et al.	2009-04-16
Method Of Forming Asymmetric Spacers And Methods Of Fabricating Semiconductor Device Using Asymmetric Spacers App 20080233691 - Cheng; Kangguo ; et al.	2008-09-25
Reduced dielectric constant spacer materials integration for high speed logic gates Grant 7,081,393 - Belyansky , et al. July 25, 2	2006-07-25
Reduced Dielectric Constant Spacer Materials Integration For High Speed Logic Gates App 20050260819 - Belyansky, Michael P. ; et al.	2005-11-24
Anisotropic and selective nitride etch process for high aspect ratio features in high density plasma Grant 6,051,504 - Armacost , et al. April 18, 2	2000-04-18

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