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Patent applications and USPTO patent grants for Wise; Michael L..The latest application filed is for "method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line contacts".
Patent | Date |
---|---|
Networked port-inventory system and method Grant 7,698,415 - Thompson , et al. April 13, 2 | 2010-04-13 |
Method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line contacts App 20040033659 - Seitz, Mihel ;   et al. | 2004-02-19 |
Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition Grant 5,915,175 - Wise June 22, 1 | 1999-06-22 |
SEC | 0001208506 | WISE MICHAEL L |
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