Williams, Kelly L.
USPTO Trademark & Patent Filings
Trademark applications and grants for Williams, Kelly L.. Williams, Kelly L. has 1 trademark applications. The latest application filed is for "THE GLASS DIVA"
- Company Aliases
- Williams, Kelly L.
- l kelly williams
- Williams; Kelly L. - Austin TX
- Williams; Kelly L. - Rochester MN
| Entity Type | INDIVIDUAL |
| Address | 2010 Heatherbrooke Rd Birmingham, ALABAMA UNITED STATES 35242 |
Trademarks Patents
| Patent Application | Date |
|---|---|
| SIDE GATE ASSIST IN METAL GATE FIRST PROCESS 20150228757 - 14/178511 Erickson; Karl R. ; et al. | 2015-08-13 |
| IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE 20150206878 - 14/672154 Erickson; Karl R. ; et al. | 2015-07-23 |
| SEMICONDUCTOR CHIP WITH POWER GATING THROUGH SILICON VIAS 20150162266 - 14/618106 Erickson; Karl R. ; et al. | 2015-06-11 |
| IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE 20150155280 - 14/093784 Erickson; Karl R. ; et al. | 2015-06-04 |
| METHOD OF IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE 20150155206 - 14/289594 Erickson; Karl R. ; et al. | 2015-06-04 |
| Side gate assist in metal gate first process 9,685,526 - 14/178,511 Erickson , et al. June 20, 2 | 2017-06-20 |
| Implementing eDRAM stacked FET structure 9,343,464 - 13/936,569 Erickson , et al. May 17, 2 | 2016-05-17 |
| Implementing buried FET utilizing drain of finFET as gate of buried FET 9,312,272 - 14/092,081 Erickson , et al. April 12, 2 | 2016-04-12 |
| Semiconductor chip with power gating through silicon vias 9,252,083 - 14/618,106 Erickson , et al. February 2, 2 | 2016-02-02 |
| Multiple-patterned semiconductor device channels 9,252,100 - 13/836,335 Allen , et al. February 2, 2 | 2016-02-02 |
Mark Image Registration | Serial | Trademark Application Date |
|---|---|
"THE GLASS DIVA" 76485389 |
THE GLASS DIVA 2003-01-28 |
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