Wille; William C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wille; William C..The latest application filed is for "methods of forming integrated circuit devices having ion-cured electrically insulating layers therein".

Company Profile

0.12.10

Wille; William C. - Red Hook NY
Wille; William C. - Red Hood NY
Wille; William C. - Poughkeepsie NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein Grant 7,838,390 - Kim , et al. November 23, 2	2010-11-23
Structure and method to form improved isolation in a semiconductor device Grant 7,635,899 - Yang , et al. December 22, 2	2009-12-22
Stress engineering using dual pad nitride with selective SOI device architecture Grant 7,550,364 - Chidambarrao , et al. June 23, 2	2009-06-23
Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein App 20090098706 - Kim; Jun-jung ; et al.	2009-04-16
Semiconductor Etching Methods App 20090047791 - Dobuzinsky; David M. ; et al.	2009-02-19
Structure And Method To Form Improved Isolation In A Semiconductor Device App 20080171420 - Yang; Haining S. ; et al.	2008-07-17
Semiconductor Structure Including Isolation Region With Variable Linewidth And Method For Fabrication Therof App 20070293016 - Luo; Zhijiong ; et al.	2007-12-20
Trench Capacitor Having Lateral Extensions In Only One Direction And Related Methods App 20070267671 - Cheng; Kangguo ; et al.	2007-11-22
Stress Engineering Using Dual Pad Nitride With Selective Soi Device Architecture App 20070122965 - Chidambarrao; Dureseti ; et al.	2007-05-31
Stress engineering using dual pad nitride with selective SOI device architecture Grant 7,202,513 - Chidambarrao , et al. April 10, 2	2007-04-10
Stress Engineering Using Dual Pad Nitride With Selective Soi Device Architecture App 20070069294 - Chidambarrao; Dureseti ; et al.	2007-03-29
Magnetic random access memory and method of fabricating thereof Grant 7,183,130 - Nuetzel , et al. February 27, 2	2007-02-27
Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material Grant 7,030,031 - Wille , et al. April 18, 2	2006-04-18
Magnetic Random Access Memory And Method Of Fabricating Thereof App 20050023581 - Nuetzel, Joachim ; et al.	2005-02-03
Method For Forming Damascene Structure Utilizing Planarizing Material Coupled With Diffusion Barrier Material App 20040266201 - Wille, William C. ; et al.	2004-12-30
Micro electromechanical switch having self-aligned spacers Grant 6,762,667 - Volant , et al. July 13, 2	2004-07-13
Micro electromechanical switch having self-aligned spacers App 20030210124 - Volant, Richard P. ; et al.	2003-11-13
Micro electromechanical switch having self-aligned spacers Grant 6,621,392 - Volant , et al. September 16, 2	2003-09-16
Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme Grant 6,461,529 - Boyd , et al. October 8, 2	2002-10-08
Field effect transistors with improved implants and method for making such transistors Grant 6,143,635 - Boyd , et al. November 7, 2	2000-11-07
Method for making field effect transistors having sub-lithographic gates with vertical side walls Grant 6,040,214 - Boyd , et al. March 21, 2	2000-03-21
Process of etching an oxide layer Grant 5,811,357 - Armacost , et al. September 22, 1	1998-09-22

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