Wilkerson; Christopher

Patent Applications and Registrations

Patent applications and USPTO patent grants for Wilkerson; Christopher.The latest application filed is for "branch prediction based on coherence operations in processors".

Company Profile

7.12.17

Wilkerson; Christopher - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Branch Prediction Based On Coherence Operations In Processors App 20200081718 - Wilkerson; Christopher ; et al.	2020-03-12
Disabling cache portions during low voltage operations Grant 10,528,473 - Wilkerson , et al. J	2020-01-07
Branch prediction based on coherence operations in processors Grant 10,521,236 - Wilkerson , et al. Dec	2019-12-31
Branch Prediction Based On Coherence Operations In Processors App 20190303162 - Wilkerson; Christopher ; et al.	2019-10-03
Apparatus And Method For Triggered Prefetching To Improve I/o And Producer-consumer Workload Efficiency App 20180373632 - WILKERSON; Christopher ; et al.	2018-12-27
Disabling Cache Portions During Low Voltage Operations App 20180060239 - WILKERSON; CHRISTOPHER ; et al.	2018-03-01
Methods and apparatuses for efficient load processing using buffers Grant 9,710,391 - Liu , et al. July 18, 2	2017-07-18
Disabling cache portions during low voltage operations Grant 9,678,878 - Wilkerson , et al. June 13, 2	2017-06-13
Semiconductor chip with adaptive BIST cache testing during runtime Grant 9,229,872 - Wilkerson , et al. January 5, 2	2016-01-05
Reducing minimum operating voltage through hybrid cache design Grant 8,868,836 - Khellah , et al. October 21, 2	2014-10-21
Semiconductor Chip With Adaptive BIST Cache Testing During Runtime App 20140281254 - WILKERSON; Christopher ; et al.	2014-09-18
Disabling Cache Portions During Low Voltage Operations App 20140108733 - Wilkerson; Christopher ; et al.	2014-04-17
Methods And Apparatuses For Efficient Load Processing Using Buffers App 20130246712 - LIU; WEI ; et al.	2013-09-19
Disabling cache portions during low voltage operations Grant 8,291,168 - Wilkerson , et al. October 16, 2	2012-10-16
Disabling Cache Portions During Low Voltage Operations App 20120110266 - Wilkerson; Christopher ; et al.	2012-05-03
Disabling cache portions during low voltage operations Grant 8,103,830 - Wilkerson , et al. January 24, 2	2012-01-24
Efficient systems and methods for consuming and providing power App 20100257529 - Wilkerson; Christopher ; et al.	2010-10-07
Disabling Cache Portions During Low Voltage Operations App 20100082905 - Wilkerson; Christopher ; et al.	2010-04-01
Reducing minimum operating voltage through hybrid cache design App 20090172283 - Khellah; Muhammad M. ; et al.	2009-07-02
Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately Grant 6,954,848 - Rakvic , et al. October 11, 2	2005-10-11
Method and system to identify slowable instructions App 20030126412 - Rakvic, Ryan ; et al.	2003-07-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.